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InnoPhase IoT
San Jose, CA, United States
Job Description: Join Innophase IoT group as a hands-on PHY Verification Engineer and be responsible for Low-power WiFi, BT/BLE verification. You will be involved in the design development cycle, which includes participating in high-level product specifications, UVM Testbench design, test planning, working closely with Systems, SW, and design eng
Job Source: InnoPhase IoTSamsung Electronics GmbH
San Jose, CA, United States
Advancing the World’s Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering t
Job Source: Samsung Electronics GmbHConductor
San Jose, CA, United States
What You’ll Do Do you want to be part of world class team with flexibility of a startup? Are you able to incubate new ideas and drive them to closure in the physical layer? As a Staff Wireless PHY Standards Architect, you will be responsible for driving and designing the next generation of physical layer for wireless technologies. You will get to
Job Source: ConductorSK hynix America
San Jose, CA, United States
Description Job Title : Staff Engineer / Sr. Staff Engineer - Pathfinding Design & Architecture Location : Sacramento CA or San Jose CA Job Type : Full-Time In the rapidly growing NAND Flash space amid the era of big data, this is an exciting time to be at SK Hynix NAND America. SK Hynix NAND America is looking for a talent that has a strong ba
Job Source: SK hynix AmericaGroq
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At Groq. We believe in an AI economy powered by human agency. We envision a world where AI is accessible to all, a world that demands processing power that is better, faster, and more affordable than is available today. AI applications are currently constrained by the limitations of the Graphics Processing Unit (GPU), a technology originally devel
Job Source: GroqArray Labs Inc.
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Array Labs is building a distributed radar imaging constellation to power the first accurate, real-time 3D model of the world. The Hardware Engineering team at Array Labs is responsible for the analysis and design of our satellite and ground-station hardware platforms. These platforms tend to be a heterogeneous mix of various subsystems like comput
Job Source: Array Labs Inc.Activate Global, Inc.
San Jose, CA, United States
Position Summary We are seeking a self-driven and passionate individual to join our Product Development Team to deliver zero-carbon industrial heat and power with our novel solid state thermal battery. We are a tight-knit team that loves what we do. We strive to have an impact, working with humility and openness and building lifelong relationships
Job Source: Activate Global, Inc.OVT group
Santa Clara, CA, United States
Responsibilities: Design and implement module level micro-architecture Participate in top-level implementation and integration Participate in both top level and module level RTL coding, simulation, synthesis and timing closure Generate test cases for the module level and chip level. Participate in FPGA emulation and post-silicon validation. Write d
Job Source: OVT groupSan Jose, CA, United States
Staff/Sr. Staff PHY Design Engineer
Job Description:
Join Innophase IoT group as a PHY Design Engineer and be responsible for Low-power WiFi, BT/BLE micro-architecture and design. You will be involved in the design development cycle, which includes participating in high-level product specifications, RTL development, working closely with Algorithm and verification engineers.
Your specific responsibilities may include but are not limited to the following:
Develop and refine Digital Signal Processing engines for wireless communication systems.
Develop micro-architecture, and SystemVerilog RTL to meet size, timing, and power target.
Analyze, and identify bottlenecks in design and provide feedback on micro-architecture, and optimizations.
Develop, and refine design, verification and analysis tools and flows, as needed.
Work closely with Verification, and Validation teams on test-plans, coverage-analysis
Work closely with Physical Design teams to provide guidance on Floor planning, specification of constraints, and timing closure.
Required Qualifications:
BSEE or MSEE, with experience in ASIC development and/or FPGA prototyping
7+ years of experience in RTL design using Verilog, SystemVerilog
Understanding of Digital Signal Processing theory, and mapping to design
Experience in WiFi Physical Layer, and/or other Physical layer like Cellular (WiMax, LTE, NR), Bluetooth, Zigbee, UWB, and/or other Physical layer (Ethernet) technologies
Ability to work independently, and proactively identify and resolve issues.
Experience with Incisive/Excellium/VCS, Verdi, Jasper/Spyglass or equivalent tools
Experience in partitioning, synthesis, placement, timing closure for FPGA and/or ASICs
Experience with front-end design and integration tasks including lint, CDC, synthesis, and developing timing ECOs.
Enjoy debugging, and problem solving in a team environment.
Preferred Qualifications:
Experience in Low Power design development, involving multiple power, and voltage domains.
Embedded SW & HW design is a strong plus.
Experience with Python, Perl, Tcl, C/C++ and shell scripts.
Experience with lab debug, multi-team, multi-site working environment is a strong plus.
Experience with ASIC and FPGA synthesis flows utilizing industry leading flows.
Experience using PowerArtist/Joules and providing actionable feedback into design.
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Email Alert for Staff/Sr. Staff PHY Design Engineer jobs in San Jose, CA, United States
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