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Infinera
San Jose, CA, United States
CA Pay Range (Annual): $130,900.00 - $243,100.00 At Infinera, your base pay is one part of your total compensation package. Your actual base pay will depend on your skills, qualifications, experience, and location. This role may be eligible for equity grants, discretionary bonuses, or commission payments. The amount of these incentives is based on
Job Source: InfineraInfinera
San Jose, CA, United States
Staff ASIC Design Engineer page is loaded Staff ASIC Design Engineer Apply locations CA, San Jose - Office time type Full time posted on Posted 30+ Days Ago job requisition id 2023157 CA Pay Range (Annual): $130,900.00 - $243,100.00 At Infinera, your base pay is one part of your total compensat
Job Source: InfineraSynopsys
Sunnyvale, CA, United States
Senior RTL Design Engineer 50213BR USA - California - Mountain View/Sunnyvale Job Description and Requirements Our Silicon IP business is all about integrating more capabilities into an SoC-faster. We offer the world's broadest portfolio of silicon IP-predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. A
Job Source: SynopsysSynopsys
Mountain View, CA, United States
ASIC Digital Design Engineer Staff 48925BR USA - USA Job Description and Requirements Our Silicon Design & Verification business is all about building high-performance silicon chips-faster. We're the world's leading provider of solutions for designing and verifying advanced silicon chips. We design the next-generation processes and models need
Job Source: SynopsysInnoPhase
San Jose, CA, United States
About InnoPhase, Inc. INNOPHASE is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA, and Bangalore, India. We are pioneering a revolutionary 5G platform that will transform cellular network deployments. Utilizing our breakthrough, patented, w
Job Source: InnoPhaseINNOPHASE
San Jose, CA, United States
About InnoPhase, Inc. INNOPHASE is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA, and Bangalore, India. We are pioneering a revolutionary 5G platform that will transform cellular network deployments. Utilizing our breakthrough, patented, w
Job Source: INNOPHASEInnoPhase
San Jose, CA, United States
As a Staff Engineer, ASIC Digital Design, you will be working with a team of design engineers to develop novel 5G ORAN SoC products for connectivity and wireless communications. You will be contributing to micro-architecture and design of digital functional blocks based on product requirements. In addition to delivering high-quality digital solutio
Job Source: InnoPhaseSamsung Electronics GmbH
San Jose, CA, United States
Job Location SSI San Jose Main Office Category Engineering - Hardware Job Type Full-time Job # 41962 Advancing the World’s Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part
Job Source: Samsung Electronics GmbHSanta Clara, CA, United States
Responsibilities:
Design and implement module level micro-architecture
Participate in top-level implementation and integration
Participate in both top level and module level RTL coding, simulation, synthesis and timing closure
Generate test cases for the module level and chip level.
Participate in FPGA emulation and post-silicon validation.
Write design specification
Requirements: BS in Electrical or Computer Engineering or related field plus 15 years of related experience, or MS in Electrical or Computer Engineering plus 10 years of related experience
Minimum of 10 years plus of ASIC design experience with knowledge of ASIC design flow, including hands-on experience in ASIC chip design and integration.
Requires knowledge of Verilog, system Verilog, C or C++ languages, digital image processing and chip-level tape out procedure from initial PRD, design, verification, timing closure, FPGA emulation and ECO.
Knowledge of display technology is a plus
Knowledge of UVM is a plus
Knowledge of DFT(Scan/MBIST/Functional Pattern) is a plus
Annual base salary for this role in California, US is expected to be between $180,000 - $220,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.
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Email Alert for Sr. Staff ASIC Design Engineer jobs in Santa Clara, CA, United States
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