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Primary Skills:Technical Manufacturing, Failure Analysis, manufacturing, scripting, hardware debugging and fault isolation
Location: Santa Clara, CA (Onsite)
Duration: 12+ Months
Contract Type: W2
Pay Range:$35.00 - $40.00 per hour. on w2
NOTE: Role opens for Women Back to Work candidates with a career gap
Grow your skills by working with the bes
Summary
Posted: Jan 13, 2023
Role Number: 200451263
At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and unusually talented Design Verification Engineer. As a member of our dynamic gr
Design Verification Engineer
Cupertino,California,United States
Hardware
Does making the next great technology product excite you? Imagine what you could do here. At Apple, our new ideas have a way of becoming great products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of th
Title: Design Verification Engineer
Location: San Jose, CA, Austin, TX, Phoenix, AZ
Duration: 12 Months.
Pay Rate: $75 to $80/hr
Job Description:
Testbench development - System Verilog UVM and C tests
Integration/development of C tests/APIs and SW build flow
Integration/development of UVM mailboxes and HW/SW communication components
Test plan devel
Imagine what you could do here at Apple! New ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Do you love working on challenges that no one has solved yet? Bring passion and dedication to your career, and there's no telling what you could accomplish.Our Display Technologies Engineering team is wo
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpin
Role: Design Verification Engineer
Work Location: Santa Clara, CA
Background check: Mandatory
Meet and great: Mandatory
JOB DESCRIPTION:
Responsibilities:
• Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces.
• Devel
About Etched
Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and e
Job Source: Etched.ai, Inc.
Design Verification Engineer
Santa Clara, CA, United States
Looking to add DV Engineers in Irvine, San Diego and Santa Clara.
On going needs additional 10 engineers in team.
Position detail: SOC verification
Experience level : 5-20 years
Architect block and full-chip verification environments using HVLs and constrained random
techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA
○ Develop test plans and coverage metrics from specifications and write block and chip-level
tests in C,SV,UVM
○ Debug RTL and Gate simulations and work with design engineers to verify fixes.
○ Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC.
○ Replicate silicon bugs in simulation environments and validate fixes or SW workarounds.
○ Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup.
○ Evaluate latest verification methodologies and develop scripts etc. to automate verification