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Etched.ai, Inc.
Cupertino, CA, United States
About Etched Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and e
Job Source: Etched.ai, Inc.CV Library
Santa Clara, CA, United States
Role: Design Verification Engineer Work Location: Santa Clara, CA Background check: Mandatory Meet and great: Mandatory JOB DESCRIPTION: Responsibilities: • Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces. • Devel
Job Source: CV LibraryMirafra Technologies
Santa Clara, CA, United States
Looking to add DV Engineers in Irvine, San Diego and Santa Clara. On going needs additional 10 engineers in team. Position detail: SOC verification Experience level : 5-20 years Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires U
Job Source: Mirafra TechnologiesVerilab
San Jose, CA, United States
Job Summary We invite you to join our highly motivated team of consultants, providing clients with the very best in verification. You will be exposed to a diverse range of designs and application areas. We work on leading edge Audio, Automotive, Comms, Processors, Space, Video and more. You will have the opportunity to travel, present at conferen
Job Source: VerilabKaygen, Inc.
San Jose, CA, United States
As an Architect for block and full-chip verification environments, you would be responsible for designing and implementing verification strategies using advanced verification techniques. This role focuses on System-on-Chips (SOCs) that incorporate embedded CPUs and mixed signal interfaces. Key Responsibilities: Architecture Design: You will archit
Job Source: Kaygen, Inc.Apple
Cupertino, CA, United States
Design Verification Engineer Santa Clara Valley (Cupertino),California,United States Hardware At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for an outstandingly hardworking design verification eng
Job Source: AppleEdacafe
Milpitas, CA, United States
This is a full-time on-site role for a Design Verification Engineer located in Milpitas, CA. The Design Verification Engineer will be responsible for formal verification, RTL design, computer architecture, functional verification, and debugging. Qualifications Experience in formal verification, RTL design, and computer architecture Experience in fu
Job Source: EdacafeDiverse Lynx
San Jose, CA, United States
Hello We are hiring for below role ! Role: Pre-Silicon Verification Engineers Experience (Years):8-10 Location: San Jose, CA Duration: 12+ Months Keywords: Pre-Silicon Validation PCIe (Gen 5) and NVMe experience, SV and UVM Role Description:- Perform pre-silicon validation for customer's flagship silicon Liaise with design teams Communicate an
Job Source: Diverse LynxSan Jose, CA, United States
Title: Design Verification Engineer
Location: San Jose, CA, Austin, TX, Phoenix, AZ
Duration: 12 Months.
Pay Rate: $75 to $80/hr
Job Description:
Testbench development - System Verilog UVM and C tests
Integration/development of C tests/APIs and SW build flow
Integration/development of UVM mailboxes and HW/SW communication components
Test plan development
Power Aware testbench development and simulations
Seamless porting between simulation/emulation/prototyping platforms
Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto
Coverage collection and closure
Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope
Engage with the team to drive continuous improvement to the verification environment to find more bugs and improve coverage
Work as a team to grow together.
Mentor and coach junior team members
Heres what you need:
A minimum of three years of experience with SoC Design Verification
Bachelors Degree or equivalent (12 years) work experience (If an, Associates Degree with 6 years of work experience)
Skills: CPU, Cortex/ARM Cortex, UVM, Verilog, Test Bench
Intelliswift Software is an Equal Employment Opportunity (EEO) employer and does not discriminate on the basis of age, color, national origin, citizenship status, physical or mental disability, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, genetic information, marital status, status with regard to public assistance, veteran status or any other characteristic protected by federal, state or local law.
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Email Alert for Design Verification Engineer jobs in San Jose, CA, United States
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