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IC Resources
San Jose, CA, United States
Join one of the world's foremost RISC-V companies as a Design Verification Engineer, contributing to the development of cutting-edge CPU products for applications such as 5G, AI, and machine learning. As a top company they offer competitive compensation, benefits, and full remote working options (they also have offices in San Jose & Portland if you
Job Source: IC ResourcesAdvanced Micro Devices
San Jose, CA, United States
WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpi
Job Source: Advanced Micro DevicesApple Inc.
Sunnyvale, CA, United States
Do you have a passion for invention and self-challenge? Do you thrive on pushing the limits of what’s considered feasible?As part of our team, you will be responsible for and contribute to verifying high-throughput, complex cellular baseband modems and transceiver link controllers: You will be crafting highly reusable premier UVM test benches, impl
Job Source: Apple Inc.Apple
Cupertino, CA, United States
Design Verification Engineer Cupertino,California,United States Hardware Does making the next great technology product excite you? Imagine what you could do here. At Apple, our new ideas have a way of becoming great products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of th
Job Source: AppleEdacafe
Milpitas, CA, United States
This is a full-time on-site role for a Design Verification Engineer located in Milpitas, CA. The Design Verification Engineer will be responsible for formal verification, RTL design, computer architecture, functional verification, and debugging. Qualifications Experience in formal verification, RTL design, and computer architecture Experience in fu
Job Source: EdacafeApple, Inc.
Sunnyvale, CA, United States
Summary Posted: Jun 10, 2024 Role Number: 200451793 Do you have a passion for invention and self-challenge? Do you thrive on pushing the limits of what's considered feasible? As part of our team, you will be responsible for and contribute to verifying high-throughput, complex cellular baseband modems and transceiver link controllers: You will be
Job Source: Apple, Inc.eTeam, Inc.
San Jose, CA, United States
Job Title: Verification Engineer Location: San Jose, CA POSITION SUMMARY QUALIFICATIONS: Education Requirements •BS/MS in EE/CE, plus 5+ years of Design Verification experience •Familiarity with ASIC, Computer and Embedded Systems Architectures •Excellent oral and written communication skills with people at all levels, a must. •Team player, with ex
Job Source: eTeam, Inc.Mirafra Technologies
Santa Clara, CA, United States
Looking to add DV Engineers in Irvine, San Diego and Santa Clara. On going needs additional 10 engineers in team. Position detail: SOC verification Experience level : 5-20 years Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires U
Job Source: Mirafra TechnologiesSan Jose, CA, United States
As an Architect for block and full-chip verification environments, you would be responsible for designing and implementing verification strategies using advanced verification techniques. This role focuses on System-on-Chips (SOCs) that incorporate embedded CPUs and mixed signal interfaces.
Key Responsibilities:
Architecture Design: You will architect block and full-chip verification environments using Hardware Verification Languages (HVLs) and constrained random techniques. This involves utilizing industry-standard methodologies like Universal Verification Methodology (UVM), System Verilog, and assertion-based verification (SVA).
Test Development: Develop comprehensive test plans and coverage metrics based on design specifications. Write block-level and chip-level tests using a combination of C, System Verilog (SV), and UVM.
Simulation and Debugging: Debug RTL (Register Transfer Level) and Gate-level simulations to identify and resolve issues. Collaborate closely with design engineers to verify and validate fixes in the design.
Bug Replication and Validation: Replicate silicon bugs in simulation environments and validate fixes or software workarounds. This involves a deep understanding of the design and its intended functionality.
ATE Vector Bringup Support: Convert verification tests into test patterns suitable for Automatic Test Equipment (ATE). Assist Test Engineers in the setup and validation of ATE vectors.
Methodology Evaluation and Automation: Stay updated with the latest verification methodologies and tools. Develop scripts and automation flows to streamline verification processes and improve efficiency.
Required Skills:
Proficiency in HVLs such as System Verilog and methodologies like UVM.
Experience with constrained random verification techniques.
Strong understanding of SOC architectures, embedded CPUs, and mixed signal interfaces.
Ability to develop test plans, coverage metrics, and verification tests.
Expertise in debugging RTL and Gate-level simulations.
Familiarity with ATE vector bringup and test pattern conversion.
Scripting skills for automation (e.g., Python, Perl) are desirable.
Preferred Qualifications:
Prior experience in verifying complex SOC designs.
Knowledge of industry-standard tools and methodologies for verification.
Strong analytical and problem-solving skills.
Ability to work effectively in a collaborative team environment.
This role requires a deep technical understanding of verification methodologies and the ability to apply them to complex SOC designs. You will play a critical role in ensuring the functional correctness and quality of the SOC products through rigorous verification processes.
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Email Alert for Design Verification Engineer jobs in San Jose, CA, United States
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