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Mastech Digital
Austin, TX, United States
Job Title : Design Verification Engineer Location: Austin, TX Requirements • 5-15 year’s industry experience in a design verification role. • Proficient in System Verilog/UVM/OVM, OOP/C++ • Knowledge of GPU, experience with Shader, Texture, or Memory System a plus • Experience with code coverage and functional coverage driven verification method
Job Source: Mastech DigitalApple, Inc.
Austin, TX, United States
Summary Posted: Mar 4, 2024 Role Number: 200455268 Does making the next great technology product excite you? Imagine what you could do here. At Apple, our new ideas have a way of becoming great products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of that team there's no tel
Job Source: Apple, Inc.Ursus Inc
Austin, TX, United States
JOB TITLE: Design Verification Engineer LOCATION: Austin, TX DURATION: 1 year PAY RANGE: $90 - $120/hr TOP SKILLS: • Current state-of-the-art testbench development such as UVM methodology • Experience in design verification with UVM and SystemVerilog is a MUST • 5-15 year's industry experience in a design verification role. COMPANY: Our client, a
Job Source: Ursus IncIntel Corporation
Austin, TX, United States
Design Verification Engineer page is loaded Design Verification Engineer Apply locations US, Texas, Austin time type Full time posted on Posted 2 Days Ago job requisition id JR0257198 Job Details: Job Description: Do Something Wonderful! Intel put the Silicon in Silicon Valley. No one else
Job Source: Intel CorporationIntel GmbH
Austin, TX, United States
Job Description Do Something Wonderful! Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are buil
Job Source: Intel GmbHCorrect Designs
Austin, TX, United States
Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position along with long term stability and benefits? Correct Designs can give it all to you. Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin,
Job Source: Correct DesignsBayone
Austin, TX, United States
- Local to Austin Market - No H1B candidate - Top 2 candidates per suppliers As a member of our System IP team you will contribute to the functional verification of System IP including coherent interconnect, and executing Test plan. Work with DV team and designers to build verification environments. Develop UVM sequences, tests, scoreboards, monit
Job Source: BayoneVoragotech
Austin, TX, United States
Do you love Space and want to leave your technical mark on exploring mankind’s next frontier? Does being a part of working with clients designing the next state-of-the-art spacecraft for near-earth orbit, Mars, Lunar and deep space explorations inspire you? Investment in Space organizations is at an all-time high, and you could have a seat at the t
Job Source: VoragotechAustin, TX, United States
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for an unusually hardworking design verification engineer. As a member of our multifaceted group, you will have the rare and great opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day.This role is for a DV engineer who will enable us to produce fully functional first silicon for Analog/Digital mixed-signal designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
Key Qualifications
Advanced knowledge of SystemVerilog and UVM
Experience developing scalable and portable test-benches
Experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, gate level simulations
Experience with serial protocols such as PCIe or USB
Experience with IP verification method
Deep knowledge with IPs developments such as PHYs, PLLs etc.
In lieu of UVM knowledge, C/C++ experienced level knowledge
Excellent knowledge of one of the scripting languages: Python, Perl, TCL
Proven knowledge of formal verification methodology
Description In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are expected to: Develop detailed test and coverage plans based on the micro-architecture Develop verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Develop verification plans for all features under your care. Execute verification plans, including design bring-up, DV environment bring-up, regression enabling all features under your care, and debug of the test failures. Develop block, IP and SoC level test-benches Track and report DV progress using a variety of metrics, including bugs and coverage. Develop IP simulation environment, and work closely with analog team to ensure overall bug-free IP design.
Education & Experience
BS degree in technical discipline with minimum 10 years of relevant experience.Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.
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Design Verification Engineer jobs in Austin, TX, United States
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