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Mastech Digital Inc.
Phoenix, AZ, United States
Mastech Digital provides digital and mainstream technology staff as well as Digital Transformation Services for all American Corporations. We are currently seeking a Physical Design Engineer for our client in the IT-Services domain. We value our professionals, providing comprehensive benefits and the opportunity for growth. This is a Contract
Job Source: Mastech Digital Inc.Mastech Digital, Inc.
Phoenix, AZ, United States
Mastech Digital provides digital and mainstream technology staff as well as Digital Transformation Services for all American Corporations. We are currently seeking a Physical Design Engineer for our client in the IT-Services domain. We value our professionals, providing comprehensive benefits and the opportunity for growth. This is a Contract
Job Source: Mastech Digital, Inc.Intel GmbH
, AZ, United States
Job Description At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. You will directly drive and work with DE cross teams to ensure that design-kits for customer enablement are lead cutting edge technologies. In addition, you will work with our customers to outline and collaborat
Job Source: Intel GmbHIntel GmbH
Phoenix, AZ, United States
Job Description Designs, develops, tests, and debugs software tools, flows, and methodologies used in design automation and by teams in the design of hardware products, process design, or manufacturing. Responsibilities include capturing user stories/requirements, writing both functional and test code, automating build and deployment, and/or perfor
Job Source: Intel GmbHEnergy Jobline CVL
Phoenix, AZ, United States
Duration:0-8 month(s) Description/Comment:LEVEL 9 CM&T Electrical Engineering - Design Integrated Circuits (IC) that power everyday electronic devices. Design custom or semi-custom silicon used on electronic devices, cloud infrastructure, machine learning, and AI computational platforms. Work across the entire silicon design lifecycle, includin
Job Source: Energy Jobline CVLEnergy Jobline CVL
Phoenix, AZ, United States
Duration:0-8 month(s) Description/Comment:LEVEL 9 CM&T Electrical Engineering - Design Integrated Circuits (IC) that power everyday electronic devices. Design custom or semi-custom silicon used on electronic devices, cloud infrastructure, machine learning, and AI computational platforms. Work across the entire silicon design lifecycle, includin
Job Source: Energy Jobline CVLIntel Corporation
, AZ, United States
GPU Physical Design Engineer page is loaded GPU Physical Design Engineer Apply locations US, California, Folsom US, California, Santa Clara US, Texas, Austin US, Arizona, Phoenix time type Full time posted on Posted 3 Days Ago job requisition id JR0259600 Job Details: Job Description: J
Job Source: Intel CorporationIntel Corporation
Phoenix, AZ, United States
Physical Design Integration Engineer page is loaded Physical Design Integration Engineer Apply locations US, Arizona, Phoenix time type Full time posted on Posted 2 Days Ago job requisition id JR0257751 Job Details: Job Description: Do Something Wonderful! Intel put the Silicon in
Job Source: Intel CorporationPhoenix, AZ, United States
Job Details:
Job Description: Do Something Wonderful!
Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below!
Life at Intel
Diversity at Intel
As a Physical Design Engineer your responsibilities include but not limited to:
Execute on Fusion Compiler synthesis flow, Auto Place and Route, Timing Performance validation, and Reliability validation which includes Layout Verification and DRC convergence, IP Integration Flows
Partner with the DA team on innovation and initiatives to enhance existing automation, tools, and methodology.
Identify and analyze problems, plans, tasks, and solutions
Perform in a dynamic and challenging environment with drive and creativity
Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate must have a bachelor's degree in electrical engineering, computer engineering, computer science, or any STEM related field with 4+ years of experience - OR - master's degree in electrical engineering, computer engineering, computer science, or any STEM related field with 3+ years of experience in two or more of the following:
Synopsys or Cadence design (RTL to GDS) tools.
Synopsys-Primetime.
ICV or Calibre DRC/LVS Layout cleanup
Preferred Qualifications:
Experience with STA at both partition and SOC level
Synopsys design (RTL to GDS) construction and signed off tools.
Strong analytical ability, problem solving and communication skills.
Ability to work independently and at various levels of abstraction.
Experience in Perl, TCL/Tk programming.
Experience with TFM (Tools, Flows, Methodology) Development
Job Type: Experienced Hire
Shift: Shift 1 (United States of America)
Primary Location: US, Arizona, Phoenix
Additional Locations: US, California, Folsom, US, California, Santa Clara, US, Oregon, Hillsboro
Business group: IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.
Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
Annual Salary Range for jobs which could be performed in
US, California:$119,130.00-$178,690.00
S al ary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
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Physical Design Engineer jobs in Phoenix, AZ, United States
ⓘ There was an unexpected error processing your request.
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