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Intel
Phoenix, AZ, United States
Job Details: Job Description: Do Something Wonderful! The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected dev
Job Source: IntelMastech Digital
Phoenix, AZ, United States
Job Description Job Description Mastech Digital provides digital and mainstream technology staff as well as Digital Transformation Services for all American Corporations. We are currently seeking a Physical Design Engineer for our client in the IT-Services domain. We value our professionals, providing comprehensive benefits and the opportun
Job Source: Mastech DigitalIntel GmbH
, AZ, United States
Job Description At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. You will directly drive and work with DE cross teams to ensure that design-kits for customer enablement are lead cutting edge technologies. In addition, you will work with our customers to outline and collaborat
Job Source: Intel GmbHIntel
Phoenix, AZ, United States
Job Details: Job Description: Do Something Wonderful! Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at
Job Source: IntelIntel Corporation
, AZ, United States
GPU Physical Design Engineer page is loaded GPU Physical Design Engineer Apply locations US, California, Folsom US, California, Santa Clara US, Texas, Austin US, Arizona, Phoenix time type Full time posted on Posted 3 Days Ago job requisition id JR0259600 Job Details: Job Description: J
Job Source: Intel CorporationIntel Corporation
Phoenix, AZ, United States
Physical Design Integration Engineer page is loaded Physical Design Integration Engineer Apply locations US, Arizona, Phoenix time type Full time posted on Posted 2 Days Ago job requisition id JR0257751 Job Details: Job Description: Do Something Wonderful! Intel put the Silicon in
Job Source: Intel CorporationIntel GmbH
Phoenix, AZ, United States
Job Description Do Something Wonderful! Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at Intel, we are bu
Job Source: Intel GmbHIntel GmbH
, AZ, United States
Job Description At Intel, Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products in the marketplace. You will directly drive and work with DE cross teams to ensure that design-kits for customer enablement are lead cutting edge technologies. In addition, you will work with our customers to outline and collaborat
Job Source: Intel GmbHPhoenix, AZ, United States
Mastech Digital provides digital and mainstream technology staff as well as Digital Transformation Services for all American Corporations. We are currently seeking a Physical Design Engineer for our client in the IT-Services domain. We value our professionals, providing comprehensive benefits and the opportunity for growth. This is a Contract position, and the client is looking for someone to start immediately.
Duration: 6+ Months Contract
Location: Phoenix, AZ
Role: Physical Design Engineer
Primary Skills: Engineering
Role Description: As a Physical Design Engineer , you must have at least 8+ years of experience. Electrical Engineering - Design Integrated Circuits (IC) that power everyday electronic devices.
- Design custom or semi-custom silicon used on electronic devices, cloud infrastructure, machine learning, and AI computational platforms.
- Work across the entire silicon design lifecycle, including system architecture, design verification, RTL digital design, physical design, design for test (DFT), and Emulation.
- BS in Computer Science or Electrical Engineering
- 3-7 years’ experience in semiconductor design and development.
Must-Have Skills:
- 3-7 years of experience required for each skill.
- Electrical Engineering
- Electronic Design Automation (EDA)
- Semiconductor Design & Development
Nice-To-Have Skills:
- Experience running power analysis in vector and vector-less modes and achieving optimal QoR on low power designs.
- Knowledge of static timing analysis, power analysis and concepts, defining timing and power constraints exceptions, switching activity definitions and simulation vectors.
- Experience with power integrity analysis at block level or top level, including EM, IR & ESD analysis, power reduction techniques in SOC design.
Responsibilities:
- Develop own physical design implementation of multi hierarchy low power designs including physical aware logic synthesis, design for testability, static timing analysis, power analysis, IR Drop, EM, in advanced technology nodes
- Resolve power issues related to physical design, identify potential low power solutions, drive execution and methodology improvements.
- Perform comprehensive power analysis in vector and vector-less modes of ASIC SoC design.
Here’s what you need:
- A minimum of three years of experience with:
o RTL2GDSllon advanced technology nodes (7nm and below)
o Low power implementation and signoff, power gating, multiple voltage rails, UPF/CPF.
o Power constraints generation and validation, power analysis, interface with power integrity analysis tools.
o TCL, Python and/or Perl programming
o EDA tools like DesignCompiler/Genus, Primetime/PrimePower, ICC2/Innovus, Redhawk/Voltus
- Bachelor’s Degree or equivalent (12 years) work experience (If an, Associate’s Degree with 6 years of work experience)
Bonus points if:
- Experience running power analysis in vector and vector-less modes and achieving optimal QoR on low power designs.
- Knowledge of static timing analysis, power analysis and concepts, defining timing and power constraints exceptions, switching activity definitions and simulation vectors
- Experience with power integrity analysis at block level or top level, including EM, IR & ESD analysis, power reduction techniques in SOC design.
Education: Bachelor’s degree in Computer Science, Electrical/Electronic Engineering, Information Technology or another related field or Equivalent
Experience: Minimum 8+ years of experience
Relocation: This position will not cover relocation expenses
Travel: No
Local Preferred: Yes
Note: Must be able to work on a W2 basis (No C2C)
Recruiter Name: Aakash Chauhan
Recruiter Phone: (412)-784-6467 (Ext: 2842)
Equal Employment Opportunity
Physical Design Engineer jobs in Phoenix, AZ, United States
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