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Tokyo Electron Limited
Austin, TX, United States
Senior ASIC Design Engineer page is loaded Senior ASIC Design Engineer Apply locations Austin / Headquarters time type Full time posted on Posted 3 Days Ago job requisition id R24-01853 Let’s search for your next career at TEL. Use the form below to search our current opportunities and then apply. Please cons
Job Source: Tokyo Electron LimitedMeta
Austin
**Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, foc
Job Source: MetaMeta
Austin
**Summary:** Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps and services like Messenger, Instagram, and WhatsApp further empowered billions around the world. Now, Meta is moving
Job Source: MetaMeta
Austin
**Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, foc
Job Source: MetaMeta
Austin
**Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, foc
Job Source: MetaAmazon
Austin
Description Join the team which delivers highly differentiated silicon into Blink and Ring battery powered devices. Our team works on state-of-the art SoCs in a vertically integrated team environment to deliver products our customers love. Drive early architectural and micro-architectural trade-offs to reduce time-to-revenue by shortening the time
Job Source: AmazonAmazon
Austin
Description By applying to this position, your application will be considered for all locations we hire for in the United States. In Annapurna Labs we are at the forefront of hardware co-design not just in Amazon Web Services (AWS) but across the industry. The work we do is cutting-edge and internet-scale while also being deeply important to our cu
Job Source: AmazonMeta
Austin
**Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration. We are looking for talented individuals with deep experience that span one or more of the key areas required to build successful world-class complex SoC
Job Source: MetaAustin, TX, United States
Let's search for your next career at TEL. Use the form below to search our current opportunities and then apply. Please consider joining our Talent Community so that we may continue to engage with you.
Job Description
Business Line Description:
TEL's new Integrated Circuit Design Solutions (ICDS) team is seeking a Lead Physical Design Engineer to implement cutting-edge ICs in the latest advanced-node technologies. This engineer will own all aspects of the PD flow, including new PDK bring-up, PD methodology definition, and chip implementation.
Successful candidates have experience in a wide array of design and implementation tools (custom design, synthesis, placement and routing, physical verification, etc), are comfortable with Python and TCL scripting for EDA flow creation, and can work effectively with the entire new product development team.
Job Summary:
Bring up PD tools in advanced-node PDKs
Modify PD reference flows for our design's needs
Integrate industry-standard PD tools with in-house custom PD tools
Perform top- and block-level PD for advanced-node ICs
Write constraints for new DRC rules
Utilize the newest PD tool features to improve PPA in advanced nodes
Write timing constraints
Perform chip finishing, timing and physical verification signoff, and tape-out activities
Job Qualifications:
B.S. (or equivalent) in Electrical Engineering or Computer Engineering required
B.S. with 5+ years or M.S. with 2+ years of industry experience desired
Experience taping out designs in advanced FinFET nodes required
Experience with backend EDA tools required Physical design: Innovus, ICCII
Custom layout: Virtuoso, Custom Compiler
Physical verification: Calibre, ICValidator
Experience with synthesis and timing EDA tools desired Synthesis: Genus, Design Compiler
Static timing analysis: Primetime, Certus
Good understanding of Python and TCL scripting languages required
Experience with scientific Python libraries (numpy, pandas, matplotlib, etc) desired
Excellent verbal and written communication skills
Onsite Job Location:
Austin, TX
Diversity creates an innovative culture. TEL US is an Equal Employment Opportunity / Affirmative Action employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, age, national origin, protected veteran status, disability status, sexual orientation, gender identity or expression, marital status, genetic information, or any other characteristic protected by law.
Subsidiary
TOKYO ELECTRON AMERICA, INC.
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Email Alert for Senior ASIC Design Engineer jobs in Austin, TX, United States
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