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Mastech Digital
San Jose, CA, United States
Job Description: Current state-of-the-art testbench development such as UVM methodology Experience in design verification with UVM and SystemVerilog is a MUST Responsibilities • Triage regression failures and make testbench updates • Debug functional errors in RTL model using simulation and debug tools. • Maintain efficient and clean regression st
Job Source: Mastech DigitalMastech Digital
San Jose, CA, United States
Job Title: Senior Design Verification Engineer Location : San Jose, CA or San Diego, CA (Hybrid) Contract Role Requirement: BS/MS/PhD (or equivalent experience) 12+ years of relevant experience in Verification. Must have knowledge of entire testbench , flow, setup and Assigning task Verification: Experience at all level - Block level - subsystem le
Job Source: Mastech DigitalAkraya
Santa Clara, CA, United States
Primary Skills:Technical Manufacturing, Failure Analysis, manufacturing, scripting, hardware debugging and fault isolation Location: Santa Clara, CA (Onsite) Duration: 12+ Months Contract Type: W2 Pay Range:$35.00 - $40.00 per hour. on w2 NOTE: Role opens for Women Back to Work candidates with a career gap Grow your skills by working with the bes
Job Source: AkrayaApple, Inc.
Cupertino, CA, United States
Summary Posted: Jan 13, 2023 Role Number: 200451263 At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and unusually talented Design Verification Engineer. As a member of our dynamic gr
Job Source: Apple, Inc.Apple
Cupertino, CA, United States
Design Verification Engineer Cupertino,California,United States Hardware Does making the next great technology product excite you? Imagine what you could do here. At Apple, our new ideas have a way of becoming great products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of th
Job Source: AppleIntelliswift Software Inc
San Jose, CA, United States
Title: Design Verification Engineer Location: San Jose, CA, Austin, TX, Phoenix, AZ Duration: 12 Months. Pay Rate: $75 to $80/hr Job Description: Testbench development - System Verilog UVM and C tests Integration/development of C tests/APIs and SW build flow Integration/development of UVM mailboxes and HW/SW communication components Test plan devel
Job Source: Intelliswift Software IncApple Inc.
Cupertino, CA, United States
Imagine what you could do here at Apple! New ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Do you love working on challenges that no one has solved yet? Bring passion and dedication to your career, and there's no telling what you could accomplish.Our Display Technologies Engineering team is wo
Job Source: Apple Inc.Advanced Micro Devices
San Jose, CA, United States
WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpin
Job Source: Advanced Micro DevicesSan Jose, CA, United States
Architect block and full-chip verification environments using HVLs and constrained random
techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA
○ Develop test plans and coverage metrics from specifications and write block and chip-level
tests in C,SV,UVM
○ Debug RTL and Gate simulations and work with design engineers to verify fixes.
○ Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC.
○ Replicate silicon bugs in simulation environments and validate fixes or SW workarounds.
○ Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup.
○ Evaluate latest verification methodologies and develop scripts etc. to automate verification
flows.
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Email Alert for Senior Design Verification Engineer jobs in San Jose, CA, United States
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