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USA Tech Recruitment
San Jose, CA, United States
Senior FPGA Design Engineer (Contract) Duration: 12 months I am partnered with a cutting edge startup, with strong financial backing, who are looking to bring on a Senior FPGA design engineer to develop their next generation AI hardware. Responsibilities Design and implement FPGA prototypes for hardware validation. Lead architecture definition
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Job Description: Join Innophase IoT as a Senior ASIC Design Engineer and be contribute to the development ofLow-power WiFi, BT/BLE RTL design, and implementation. You will be involved in the design development cycle, which includes participating in high-level product specifications, RTLdevelopment, working closely with RTL design and verification
Job Source: InnoPhase IoTUSA Tech Recruitment
San Jose, CA, United States
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Job Source: USA Tech RecruitmentNVIDIA
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Job Source: SpreadtrumusaInnoPhase IoT
San Jose, CA, United States
Job Description: Join Innophase IoT as a WiFI MAC Design Engineer/Lead and be responsible for Low-powerWiFi, BT/BLE micro-architecture and design. You will be involved in the design developmentcycle, which includes participating in high-level product specifications, RTL development,working closely with Algorithm and verification engineers. Your s
Job Source: InnoPhase IoTMirafra Technologies
San Jose, CA, United States
Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA ○ Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM ○ Debug RTL and Gate simulations and work with
Job Source: Mirafra TechnologiesInnoPhase IoT
San Jose, CA, United States
Staff/Sr. Staff PHY Design Engineer Job Description: Join Innophase IoT group as a PHY Design Engineer and be responsible for Low-power WiFi, BT/BLE micro-architecture and design. You will be involved in the design development cycle, which includes participating in high-level product specifications, RTL development, working closely with Algorithm
Job Source: InnoPhase IoTSan Jose, CA, United States
Senior FPGA Design Engineer - RTL / Verilog / Prototyping
We are partnered with a leading semiconductor company in the US working on cutting edge next generation AI Hardware looking to expand their team in the US with a Senior FPGA Design Engineer on a contract basis.
This is a contract opportunity based onsite in San Jose, California.
Key responsibilities for this Senior FPGA Design Engineer position:
Design and implement FPGA-based prototypes to validate critical hardware design aspects.
Lead architecture definition, RTL programming, synthesis, and timing closure for high-speed Xilinx FPGA design in AI inference acceleration.
Collaborate with hardware, software, diagnostics, and signal integrity engineers for subsystem integration and validation.
Key Requirements:
BS/MS in Electrical Engineering, Computer Engineering, or related fields with 7+ years of FPGA prototyping experience.
Strong Verilog HDL programming skills, targeting RTL for custom ASIC development on Xilinx FPGA.
Experience with Ethernet protocols, PCIe, optical transceivers, signal integrity, and system bring-up.
Basic knowledge of UNIX OS, device drivers, and scripting tools.
Keywords: FPGA Engineer / Field Programmable Gate Arrays Engineer / AI / Artificial Intelligence / Semiconductor / AI Hardware / Prototype / Prototyping / Verilog / HDL / RTL / ASIC / Ethernet / PCIe / Optical Transceivers / Signal Integrity / System Bring-Up / Unix OS / High-Speed
If you are interested in this Senior FPGA Design Engineer position, please send a CV to [email protected]
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Email Alert for Senior FPGA Design Engineer - RTL / Verilog / Prototyping jobs in San Jose, CA, United States
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