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Mountain View
Minimum qualifications: + Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. + 5 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Preferred qualifications: + Experience with image processing or other multimedia I
Job Source: GoogleGoogle Inc.
Mountain View, CA, United States
link Copy link corporate_fare Google place Mountain View, CA, USA Mid Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area. Apply link Copy link Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or
Job Source: Google Inc.Apple, Inc.
Cupertino, CA, United States
Summary Posted: Nov 14, 2023 Role Number: 200520594 Are you a leader and want to apply your engineering background to make big things happen, and can you influence, connect, get results and communicate effectively while delivering on a predictable and dynamic schedule? The Custom Silicon Management Group provides critical custom silicon for all
Job Source: Apple, Inc.Apple Inc.
Cupertino, CA, United States
Are you a leader and want to apply your engineering background to make big things happen, and can you influence, connect, get results and communicate effectively while delivering on a predictable and dynamic schedule?The Custom Silicon Management Group provides critical custom silicon for all mobile products including iPhone, iPad, iPod, and AppleT
Job Source: Apple Inc.SQL Pager LLC
San Jose, CA, United States
Job Description Full time, direct hire role at client (semiconductor company) Lead verification efforts on PCIe IPs and SoC products Architect and build system and unit-level UVM verification environment Work with architects to define verification strategy and execution plans Review metrics and deliver task with high quality Analyze Functional, Cod
Job Source: SQL Pager LLCLightmatter
Mountain View, CA, United States
Principal/Lead Design Verification Engineer Lightmatter is a photonic computer company that is redefining what computers and human beings are capable of by building the engines that will drive discoveries and progress sustainably. With modern human progress relying heavily on computers, the world has hit a dead end with traditional transistors, and
Job Source: LightmatterWestern Digital
Milpitas, California
Job Description ESSENTIAL DUTIES AND RESPONSIBILITIES: Responsible for defining and tracking test plans through product development cycles from EVT through customer qualification and MP. Monitor regression and qualification test cycles, perform first level FA and triage of failures, prepare and present testing statistics, and work closely with c
Job Source: Western DigitalSpaceX
Sunnyvale, CA, United States
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we
Job Source: SpaceXMountain View
Minimum qualifications:
+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
+ 5 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
Preferred qualifications:
+ Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
+ Experience in low-power design verification.
+ Experience with multimedia IPs such as display or video codec, accelerator IPs.
+ Experience with SOC integration and sub-system verification.
+ Experience in verification of CPU based designs and sub-systems.
+ Knowledge of Verification methodologies and formal verification.
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work on Design Verification of IP’s and Sub-systems spanning across Core IP development areas, including Multimedia, Security and Accelerators. This includes planning, testbench architecture, UVM based constrained Random testbench development, debug, coverage closure and sign-off.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
The US base salary range for this full-time position is $150,000-$223,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google (oogle.com/benefits/) .
+ Plan the verification of complex Core IP’s in Multimedia, Security and AI Accelerator blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
+ Create and enhance constrained-random verification environments using System Verilog and UVM.
+ Identify and write all types of coverage measures for stimulus and corner-cases.
+ Debug tests with design engineers to deliver functionally correct design blocks.
+ Close coverage measures to identify verification holes and show progress towards tape-out.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also oogle.com/eeo/ and oogle.com/jobs/dist/legal/OFCCP_EEO_Post.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: l/forms/aBt6Pu71i1kzpLHe2.
Email Alert for Design Verification Engineering Lead, Silicon_ jobs in Mountain View
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