Senior Physical Design Engineer

Hillsboro, OR, United States

Microsoft Corporation Senior Physical Design Engineer Hillsboro , Oregon Apply Now Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products such as Xbox to high-performance Azure cloud servers, clients, and augmented reality.

We are looking for a Senior Physical Design Engineer to work on leading edge Intellectual Property (IP) development as part of the Semi-Custom and Central Intellectual Property Silicon (SCIPS) team. The candidate should be a motivated self-starter who will thrive in this cutting-edge technical environment.

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day.

We’re committed to a diverse and inclusive workplace and encourage applicants from all backgrounds and walks of life. Difference makes us better.

Responsibilities

Microsoft’s SCIPS organization develops various soft and hard IPs and you will have the opportunity to implement designs in Register Transfer Level (RTL) to Physical Design (PD) and RTL to Graphic Data Systems (GDS) flows. For RTL-to-PD, you will be a key link between front-end design and System on Chip (SOC) back-end teams. You will be responsible for implementing feedback and mitigations in the design constraints and toolchain to ensure best-in-class Power Performance Area (PPA.) In RTL-to-GDS, you will not only be responsible for the tasks mentioned in RTL-to-PD, but also floorplanning, place-and-route, and signoff for timing, Electro Migration and Voltage Drop (EMVD), and physical verification. Excellent communication skills will be needed to coordinate with RTL, Design for Test (DFT) Computer Aided Design (CAD) and SoC physical design teams.

You will participate in flow development, design automation, and correlation exercises to back-end flows. You are expected to work with limited direction and have attention to detail. You will also be expected to be able to provide status of progress, issues, and risks on the program to the management team.

Other

Embody our Culture (https://www.microsoft.com/en-us/about/corporate-values) and Values (https://careers.microsoft.com/us/en/culture)

Qualifications

Required Qualifications:

7+ years of related technical engineering experience

OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience.

OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience.

OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

4+ years of experience in hardware design.

4+ years of experience in synthesis, timing constraints and timing closure, front-end design checks, place-and-route and PPA tradeoffs.

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check:

This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

Experience in collateral development including timing and synthesis constraints.

Experience in front-end design checks including Lint, Formal Equivalence.

Experience in recent synthesis tool capabilities.

Experience in static timing analysis.

Familiarity with RTL and gate-level power analysis/optimization, and power-intent verification.

Experience in physical/timing/electrical quality, and final signoff for large IP delivery.

Experience in using Synopsys tool (Fusion Compiler/ICC2, Primetime) commands.

Experience in translating physical design results into feedback for flow or RTL improvement.

Experience in Tcl, Perl, Python, shell programming.

Experience in full RTL-to-GDS flow.

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $112,000 - $218,400 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $145,800 - $238,600 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .

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