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Correct Designs
, ID, United States
Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position along with long term stability and benefits? Correct Designs can give it all to you. Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin,
Job Source: Correct DesignsMastech Digital
united states
Job Description Role Overview Current state of the art testbench development such as UVM methodology Experience in design verification with UVM and System Verilog is a MUST As a Design Verification Engineer, you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. Responsibilities Triage regr
Job Source: Mastech DigitalOho Group Ltd
united states
Come aboard a pioneering hardware startup in Silicon Valley as a Silicon Verification Engineer. Our mission is to revolutionize silicon by crafting Risc-V based computing platforms set to redefine the industry. Here, you'll collaborate with some of the globe's most talented and dedicated engineers, shaping designs that push the boundaries of perfor
Job Source: Oho Group LtdSynapse Design Inc.
united states
Key responsibilities: · 5+ years of working experience in Design verification. · Pre-Silicon IP validator for USB IP · The works involved subsystem-level verification. · Knowledge in test plan writing, writing tests in UVM and System Verilog, · Able to debug RTL issues, coverage writing and SVA, waveform debug using Verdi. If you're interested, pl
Job Source: Synapse Design Inc.Intelliswift Software
united states
Role: Hardware Engineer IV (Design Verification Engineer IV) Location: Redmond, WA Job Term: 12 months contract with possibility of extension (on W2) Must-Have Skills: Proven experience in designing verification test requirements within consumer electronic devices Python experience and experience with test equipment and measurement techniques to v
Job Source: Intelliswift SoftwareZenex Partners
united states
Position Title: Design Verification Engineer (GPU Subsystems) Department: Technical Location: Austin, Texas Metropolitan Area Position Type: Extendable contact for 12 month Role type : W2, C2C and 1099 Description: As a Design Verification Engineer, you will play a pivotal role in ensuring the functional verification of GPU Subsystems, including Sh
Job Source: Zenex PartnersIC Resources
united states
Join one of the world's foremost RISC-V companies as a Design Verification Engineer, contributing to the development of cutting-edge CPU products for applications such as 5G, AI, and machine learning. As a top company they offer competitive compensation, benefits, and full remote working options (they also have offices in San Jose & Portland if yo
Job Source: IC ResourcesAcceler8 Talent
united states
Acceler8 Talent has joined forces with a well-supported data center acceleration company that is actively searching for a driven Design Verification Engineer This company is deeply committed to developing a novel interconnect architecture aimed at resolving congestion challenges within extensively distributed systems. Their recent successful compl
Job Source: Acceler8 Talentunited states
Principal ASIC/SoC Verification Engineer
Role Overview
As a Principal ASIC/SoC Verification Engineer you'll play a pivotal role in verifying IP for ASIC products, including custom AI chips. This position demands expertise in IP and subsystem verification, particularly in SerDes and processor subsystems, among other IP components.
Key Responsibilities:
Architect modern verification environments and test benches.
Utilize industry-standard verification methodologies and tools, with a deep understanding of UVM, System Verilog, RTL design, and verification.
Define block and sub-system level test plans, create reusable test benches, and drive verification closure.
Perform CDC checks, formal verification, functional coverage, gate-level debug, and emulation.
Provide strong debugging and problem-solving skills to resolve complex issues under schedule pressure.
Bring expertise in SerDes systems, including architecture, protocols, and SerDes bring-up.
Apply knowledge of processor microarchitectures and bus protocols.
Contribute to the creation and management of automated verification environments.
Communicate effectively and collaborate as a team player.
Requirements:
BS/MS in EE, CS, or related field with at least 12 years of proven SoC/ASIC verification experience.
Hands-on experience in defining and implementing verification environments and test benches.
Proficiency in UVM, System Verilog, and RTL design and verification.
Experience in CDC checks, formal verification, functional coverage, gate-level debug, and emulation tools.
Familiarity with SerDes systems, processor microarchitectures, and bus protocols.
Ability to create and manage automated verification environments is advantageous.
Excellent communication skills and a collaborative team player.
Note: This position offers the opportunity to work on cutting-edge AI chip projects within a dynamic and innovative environment.
Design Verification Engineer jobs in united states
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