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Correct Designs
, ID, United States
Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position along with long term stability and benefits? Correct Designs can give it all to you. Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin,
Job Source: Correct DesignsFidelis Companies
united states
Principal ASIC/SoC Verification Engineer Role Overview As a Principal ASIC/SoC Verification Engineer you'll play a pivotal role in verifying IP for ASIC products, including custom AI chips. This position demands expertise in IP and subsystem verification, particularly in SerDes and processor subsystems, among other IP components. Key Responsibili
Job Source: Fidelis CompaniesSynapse Design Inc.
united states
Key responsibilities: · 5+ years of working experience in Design verification. · Pre-Silicon IP validator for USB IP · The works involved subsystem-level verification. · Knowledge in test plan writing, writing tests in UVM and System Verilog, · Able to debug RTL issues, coverage writing and SVA, waveform debug using Verdi. If you're interested, pl
Job Source: Synapse Design Inc.Mastech Digital
united states
Job Description Role Overview Current state of the art testbench development such as UVM methodology Experience in design verification with UVM and System Verilog is a MUST As a Design Verification Engineer, you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. Responsibilities Triage regr
Job Source: Mastech DigitalOho Group Ltd
united states
Come aboard a pioneering hardware startup in Silicon Valley as a Silicon Verification Engineer. Our mission is to revolutionize silicon by crafting Risc-V based computing platforms set to redefine the industry. Here, you'll collaborate with some of the globe's most talented and dedicated engineers, shaping designs that push the boundaries of perfor
Job Source: Oho Group LtdIC Resources
united states
Join one of the world's foremost RISC-V companies as a Design Verification Engineer, contributing to the development of cutting-edge CPU products for applications such as 5G, AI, and machine learning. As a top company they offer competitive compensation, benefits, and full remote working options (they also have offices in San Jose & Portland if yo
Job Source: IC ResourcesIntelliswift Software
united states
Role: Hardware Engineer IV (Design Verification Engineer IV) Location: Redmond, WA Job Term: 12 months contract with possibility of extension (on W2) Must-Have Skills: Proven experience in designing verification test requirements within consumer electronic devices Python experience and experience with test equipment and measurement techniques to v
Job Source: Intelliswift SoftwareIC Resources
united states
Join one of the world's foremost RISC-V companies as a Senior Verification Engineer, contributing to the development of cutting-edge CPU products for applications such as 5G, AI, and machine learning. As a top company they offer competitive compensation, benefits, and full remote working options (they also have offices in San Jose & Portland if yo
Job Source: IC Resourcesunited states
Position Title: Design Verification Engineer (GPU Subsystems)
Department: Technical
Location: Austin, Texas Metropolitan Area
Position Type: Extendable contact for 12 month
Role type : W2, C2C and 1099
Description: As a Design Verification Engineer, you will play a pivotal role in ensuring the functional verification of GPU Subsystems, including Shader, Texture, and Memory Systems. This role involves triaging regression failures, debugging functional errors in RTL models, and maintaining efficient regression status. You will contribute to the development of Scalable SystemVerilog/UVM test benches and collaborate closely with Architects and RTL designers to ensure comprehensive verification coverage.
Responsibilities:
Triage regression failures and implement necessary testbench updates.
Debug functional errors in RTL models using simulation and debug tools.
Maintain efficient and clean regression status.
Develop Scalable SystemVerilog/UVM testbenches for unit and/or Cluster level verification.
Review Architecture and Micro-Architecture specifications.
Work closely with Architects and RTL designers.
Define, maintain, and execute unit and/or Cluster level verification test plans.
Generate and execute test cases on logic simulation models.
Code Functional coverage models and System Verilog assertions.
Drive Functional Coverage and Code coverage to closure.
Integrate C++ reference models into Scoreboards.
Requirements:
5-15 years of industry experience in a design verification role.
Proficiency in System Verilog/UVM/OVM, OOP/C++.
Knowledge of GPU, and experience with Shader, Texture, or Memory Systems a plus.
Experience with code coverage and functional coverage-driven verification methodology.
Experience in creating, running, and debugging SystemVerilog/UVM constraint-random Testbenches.
Excellent working knowledge of scripting languages such as Python or Perl.
Understanding of micro-architecture, logic design, FSMs, and arithmetic datapath pipelines.
Strong functional verification experience including Test planning, Testbench Architecture, and Test/Coverage Model/Assertion Development.
Strong debugging skills.
Strong programming skills with a good understanding of algorithms and data structures.
Good verbal and written communication skills.
Additional Requirements:
Familiarity with current state-of-the-art testbench development such as UVM methodology.
Experience in design verification with UVM and SystemVerilog is a MUST.
Hybrid onsite presence is required 3 times per week.
Intrested candidates can directly call me @ 4083618408
Design Verification Engineer jobs in united states
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