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Intel Corporation
Santa Clara, CA, United States
Physical Design Applications Engineer (Design Enablement) page is loaded Physical Design Applications Engineer (Design Enablement) Apply locations US, Oregon, Hillsboro US, California, Santa Clara US, Arizona, Phoenix time type Full time posted on Posted 14 Days Ago job requisition id JR0262636 Job Details:
Job Source: Intel CorporationCadence Design Systems, Inc.
San Jose, CA, United States
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Description We offer amazing opportunities to grow, no matter where you are in your career. The ideal candidate will be energetic, innovative and enthused with how to help customers solve their toughest place and route problems using Cad
Job Source: Cadence Design Systems, Inc.Intel
Santa Clara, CA, United States
Applications Engineer Physical Design/Fill - (Design Enablement) page is loaded Applications Engineer Physical Design/Fill - (Design Enablement) Apply locations US, Oregon, Hillsboro US, California, Santa Clara US, Arizona, Phoenix time type Full time posted on Posted 2 Days Ago job requisition id JR0262670 Job Details: Job Descriptio
Job Source: IntelSynopsys
Mountain View, CA, United States
Job Description and Requirements Our Silicon Design & Verification business is all about building high-performance silicon chips-faster. We're the world's leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our custome
Job Source: SynopsysCadence Design Systems
San Jose, CA, United States
Senior Applications Engineer, DDR Design IP page is loaded Senior Applications Engineer, DDR Design IP Apply locations SAN JOSE time type Full time posted on Posted 2 Days Ago job requisition id R46222 At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Source: Cadence Design SystemsCadence Design Systems
San Jose, CA, United States
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Title Senior Applications Engineer DDR Design IP Job Location: San Jose, CA Job Description The Cadence IP team develops industry leading IPs that enable customers in a variety of markets - from the endpoint to the edge to the cloud. At Cad
Job Source: Cadence Design SystemsCadence Design Systems, Inc.
San Jose, CA, United States
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Title Senior Applications Engineer DDR Design IP Job Location: San Jose, CA Job Description The Cadence IP team develops industry leading IPs that enable customers in a variety of markets - from the endpoint to the edge to the cloud.
Job Source: Cadence Design Systems, Inc.NVIDIA Corporation
Santa Clara, CA, United States
Senior Physical Design Methodology Engineer page is loaded Senior Physical Design Methodology Engineer Apply locations US, CA, Santa Clara time type Full time posted on Posted 2 Days Ago job requisition id JR1967201 Do you have a passion for computer gaming, virtual reality, computer vision, and artificial intel
Job Source: NVIDIA CorporationSan Jose, CA, United States
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Principal Application Engineer responsible for providing pre-sales and post-sales technical support for the Digital Implementation and Signoff tools. Will work closely with customers on bringing up flows at advanced nodes, and solving challenges in meeting power, performance and area (PPA) in vertical markets such as datacenter, ML/AI, networking and processors. The position offers growth opportunities to learn different customer segment requirements, and the latest advancements in Machine learning and 3DIC.
+ Working with customers in one or more of the following areas:
Synthesis, Place and Route, timing and power signoff.
+ Understanding and proliferating Cadence flow solutions in the areas of 3DIC implementation and ML/AI based implementation
+ Driving technical evaluations/benchmarks, presenting results and delivering Cadence solutions implementations
+ Supporting adoption and proliferation at existing customers (on/offsite), to help drive business for our digital implementation tools, i.e., Genus, Innovus, Tempus or Fusion Compiler, ICC2 and Primetime.
+ Working closely with R&D on tools and methodology improvements
+ Create and contribute technical content for Cadence Online Support
The Position Requirements are
+ Bachelors degree with at least 3-6 years of design/EDA experience or Masters degree with at least 4 years of experience. Masters degree preferred.
+ Strong knowledge of Digital Design Fundamentals, Semiconductor fundamentals and Static Timing Analysis is required
+ Prior experience with ASIC digital implementation flows and EDA tools is required, RTL to GDSII ; Experience with advanced nodes (7nm and below) preferred.
+ Must have experience in a scripting language such as TCL/Perl/Python
+ Candidate should have strong customer-facing communication and problem solving skills
+ Strong personal drive for continuous learning and expanding professional skill sets
+ Strong verbal and written communication skills
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The annual salary range for California is $98,000 to $182,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
Were doing work that matters. Help us solve what others cant.
Additional Jobs (https://cadence.wd1.myworkdayjobs.com/addl_jobs)
Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.
Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. ?Our shared passion for solving the worlds toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.
Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
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Senior Physical Design Applications Engineer jobs in San Jose, CA, United States
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