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Etched
Cupertino, CA, United States
Physical Design Engineer Etched is building the hardware for superintelligence. GPUs and TPUs are flexible AI chips that can run many kinds of models: CNNs, RNNs, LSTMs, and more. But today, almost all AI workloads, from ChatGPT to self-driving cars, are done on one model architecture: transformers. Using flexible AI chips for transformers is very
Job Source: EtchedIntel Corporation
Santa Clara, CA, United States
Physical Design Applications Engineer (Design Enablement) page is loaded Physical Design Applications Engineer (Design Enablement) Apply locations US, Oregon, Hillsboro US, California, Santa Clara US, Arizona, Phoenix time type Full time posted on Posted 14 Days Ago job requisition id JR0262636 Job Details:
Job Source: Intel CorporationCadence Design Systems, Inc.
San Jose, CA, United States
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Principal Application Engineer responsible for providing pre-sales and post-sales technical support for the Digital Implementation and Signoff tools. Will work closely with customers on bringing up flows at advanced nodes, and solving chal
Job Source: Cadence Design Systems, Inc.Cadence Design Systems, Inc.
San Jose, CA, United States
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Description We offer amazing opportunities to grow, no matter where you are in your career. The ideal candidate will be energetic, innovative and enthused with how to help customers solve their toughest place and route problems using Cad
Job Source: Cadence Design Systems, Inc.Intel
Santa Clara, CA, United States
Applications Engineer Physical Design/Fill - (Design Enablement) page is loaded Applications Engineer Physical Design/Fill - (Design Enablement) Apply locations US, Oregon, Hillsboro US, California, Santa Clara US, Arizona, Phoenix time type Full time posted on Posted 2 Days Ago job requisition id JR0262670 Job Details: Job Descriptio
Job Source: IntelMacom Technology Solutions Holdings, Inc.
Santa Clara, CA, United States
MACOM designs and manufactures semiconductor products for Data Center, Telecommunication and Industrial and Defense applications. Headquartered in Lowell, Massachusetts, MACOM has design centers and sales offices throughout North America, Europe and Asia. MACOM is certified to the ISO9001 international quality standard and ISO14001 environmental ma
Job Source: Macom Technology Solutions Holdings, Inc.Marvell Semiconductor
Santa Clara, CA, United States
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire i
Job Source: Marvell SemiconductorOracle
Redwood City, CA, United States
Job Description Analyze, design develop, troubleshoot and debug software programs for commercial or end user applications. Writes code, completes programming and performs testing and debugging of applications. The ERP Cloud Application Development team is looking for passionate, innovative, high caliber, team oriented Engineer that seek being a m
Job Source: OracleMountain View, CA, United States
Job Description and Requirements
Our Silicon Design & Verification business is all about building high-performance silicon chips-faster. We're the world's leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance-eliminating months off their project schedules.
We're looking for Physical Design Specialist (PDS) to join the team.
Does this sound like a good role for you?
In this role you would be:
The primary focus of the Physical Design Specialist (PDS) is to support the sale and adoption of Synopsys Implementation products to help customers achieve tangible and lasting performance improvements in the cost, quality, and development time for projects. PDS are expected to possess Place & Route (physical), Synthesis (logical and physical), STA experience and knowledge. PDS AEs are expected to be knowledgeable in multiple domains of design implementation and understand codependency of flow and methodology such as Macro & Standard Cell Placement, Clock Tree Synthesis, Routing, Advanced Timing Optimization techniques . Additional knowledge of RTL Coding, Synthesis, Equivalency check, Constraints (timing & Power) is preferable.
In addition, PDS AEs will articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2). Development time will be spent gaining expertise in additional, or specialization tools, broadening focus from product emphasis to methodology, sharpening Account Management skills, and learning to leverage success.
PDS AEs are expected to manage multiple customer activities concurrently, and work with Account Managers and AE management to set their priorities. Sales support roles include product demonstrations, evaluations, and competitive benchmarking. Customer support roles include training, problem resolution, and technical account management. PDS AEs must be able to interact effectively with end-users at customer sites, as well as first level managers. PDS AEs also participate in account planning, where they work as part of the account team to develop the Synopsys solution to customer problems by bringing their understanding of customers' needs and issues.
Key Qualifications: Design experience should include ASIC design using industry-standard tools (Synthesis, Placement, Optimization, CTS, Routing)
RTL to GDSII full flow experience or knowledge is preferable.
Strong interest and understanding of Advanced Node & Design methodologies are required.
Deep Synopsys Back-end tool (Logical and Physical Synthesis, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis) experience and knowledge are required.
Excellent verbal and written presentation/communication skills are mandatory. Customer sensitivity, the ability to multiplex many issues & set priorities, and the desire to help customers exploit new technologies are essential for success in the position.
Preferred Experience: BSEE or equivalent, required with 8+ years of experience, or MSEE, or equivalent with 6+ years of experience.
Tool knowledge expected: Backend P&R tools (e.g. Fusion Compiler, ICC2 or Other PnR tools )
Tool knowledge (preferred): front end Synthesis tools (Fusion Compiler, Design Compiler)
Tool knowledge (preferred): STA (Primetime)
#LI-DP1
The base salary range across the U.S. for this role is between $173,000-$259,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
Principal Applications Engineer, Physical Design Specialist jobs in Mountain View, CA, United States
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