Physical Design Engineer

Folsom, CA, United States

The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people’s digital lives. Come join us and do something wonderful!

Who We Are

We are the Intel CEG DDR Structural Design team driving the future of DDR technologies with Intel. We deliver custom analog and mixed signal layout designs for current and next generation DDR designs which are used across Intel's spectrum of products, including client CPUs, Server CPUs, and/or other domains.

Who You Are

The Physical Design Engineer drives integration of analog and mixed signal IPs and highspeed interfaces into subsystems or analog components and partners with package and platform teams on analog integration. Supports pathfinding studies in silicon development and relays feedback to silicon and packaging team on analog integration and tradeoffs. Guides the integration process from specification documentation to silicon tapeout and provides debugging support for analog functionality related debugs in the product. Possesses expertise in design verification flows, packaging effects, and integration flows to resolve integration challenges involved in mixed signal designs and deliver optimum performance of the overall circuit. Works closely with analog IP, SoC architecture, SoC design, package, and platform design functions to meet the analog specification for the product.

Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications :

Possess a Master’s degree in Electrical Engineering or equivalent AND

4+ years of experience in the following:

Experience in Floorplanning (preferably in complex Mixed-Signal blocks involving multiple analog blocks)

Experience in debug of LVS, DRC and other layout verification flows

Experience in one or more of the follow industry standard tools (eg. Fusion Compiler, Primetime, Conformal etc.)

Experience in one or more of the following scripting languages (eg. TCL, Perl, Python etc.)

Preferred Qualifications:

6+ years of experience in Physical Design

Synthesis and PNR flows on designs with greater than 500k instances

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Job Type: Experienced Hire Job Details: Job Description:  Do Something Wonderful!

The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people’s digital lives. Come join us and do something wonderful!

Who We Are

We are the Intel CEG DDR Structural Design team driving the future of DDR technologies with Intel. We deliver custom analog and mixed signal layout designs for current and next generation DDR designs which are used across Intel's spectrum of products, including client CPUs, Server CPUs, and/or other domains.

Who You Are

The Physical Design Engineer drives integration of analog and mixed signal IPs and highspeed interfaces into subsystems or analog components and partners with package and platform teams on analog integration. Supports pathfinding studies in silicon development and relays feedback to silicon and packaging team on analog integration and tradeoffs. Guides the integration process from specification documentation to silicon tapeout and provides debugging support for analog functionality related debugs in the product. Possesses expertise in design verification flows, packaging effects, and integration flows to resolve integration challenges involved in mixed signal designs and deliver optimum performance of the overall circuit. Works closely with analog IP, SoC architecture, SoC design, package, and platform design functions to meet the analog specification for the product.

Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications :

Possess a Master’s degree in Electrical Engineering or equivalent AND

4+ years of experience in the following:

Experience in Floorplanning (preferably in complex Mixed-Signal blocks involving multiple analog blocks)

Experience in debug of LVS, DRC and other layout verification flows

Experience in one or more of the follow industry standard tools (eg. Fusion Compiler, Primetime, Conformal etc.)

Experience in one or more of the following scripting languages (eg. TCL, Perl, Python etc.)

Preferred Qualifications:

6+ years of experience in Physical Design

Synthesis and PNR flows on designs with greater than 500k instances

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location:  US, Arizona, Phoenix Additional Locations: US, California, Folsom, US, California, Santa Clara Business group: The Client Engineering group (CEG) is a worldwide organization focused on the development and integration of SOCs, and critical IPs that power Intel's leadership products, driving the Client roadmap for CCG, and invest in future disruptive technologies. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Annual Salary Range for jobs which could be performed in

US, California:$144,501.00-$217,311.00 S al ary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

Intel provides reasonable accommodation to applicants and employees. For more information on our Reasonable Accommodation process, please click here .

To view our candidate privacy notice, please click here .

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