Design Verification Engineer

San Diego, CA, United States

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Do you have a passion for invention and self-challenge? Do you thrive on pushing the limits of what’s considered feasible?As part of our team, you will be responsible for and contribute to verifying high-throughput, complex cellular baseband modems and transceiver link controllers: You will be crafting highly reusable premier UVM test benches, implementing coverage driven and directed test cases working with cross functional teams, deploying new tools and methodologies to improve quality of tape-out readiness. By collaborating with other product development groups across Apple, you’ll push the industry boundaries of what cellular systems can do and improve the product experience for our customers across the world! You will be able to learn different aspects of cellular protocol, different complex IPs and Sub-system architectures, different fabric protocols and architecture, best in class DV methodology, co-verification with models and FW, industry standard low-power architecture and complex debug architectures, etc. You will have a dedicated/hands-on ASIC DV experience in reusable verification methodology such as UVM or OVM.As a Design Verification Engineer in our team, you are at the center of the verification effort within our silicon design group! You will be designing and productizing state-of-the-art cellular baseband modems and RF link controllers targeted for SOCs. You are responsible for high quality verification of different complex IPs and Sub-System designs by working closely with cross-functional teams. You are expected to adapt to evolving requirements, do detail test planning and develop re-usable verification environments to achieve quality goals.

Description

Once you understand the details of design components and any associated system reference models. You will construct detailed test plan for various components of the design including use cases, through collaborative work with cross-functional teams. You will create coverage driven verification plans from specifications, review with multi-functional teams and refine to achieve coverage targets. Architect UVM-based, reusable test benches with components for stimulus, checkers, VIPs and reference models. Work closely with DV methodology architects to improve verification flow. Execute test plan from RTL simulation bring-up to sign-off, report and debug failures, maintain regressions, report verification progress against test plan and coverage metrics.

Minimum Qualifications

Key Qualifications

BS and 3+ years of relevant industry experience.

Strong knowledge of System Verilog and UVM

Good understanding of System C, C/C++, Python/perl

Experience in developing and establishing DV Methodologies

Ability to develop System Verilog Testbench with UVM methodology from scratch

Experience in C/C++ modeling for design verification is a plus

Experience with constraint random testing, SVA, Coverage driven verification

Good test planning and problem-solving skills

Knowledge of 4G/5G cellular physical layer operation (3GPP) is a plus

Experience with verification of embedded processor cores

Hands-on verification experience of Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment

Should be a standout colleague with excellent communication and analytic skills with the desire to take on diverse challenges.

Preferred Qualifications Education & Experience

BS and 3+ years of relevant industry experience.

Additional Requirements

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $131,500 and $243,300, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.

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