Analog Design Engineer

Folsom, CA, United States

Job Details: Job Description: Role and Responsibilities:

We are looking for a highly motivated analog designer to join the circuit team for Intel's next generation of chipsets/SOC. As part of the team, you will be working across different teams within the organization: architecture, technology development, IP designers, package and platform engineers to analyze different technology nodes and influence process decision for the SOC.

Responsibilities of this role include, but are not limited to:

Analysis and alignment with internal/external foundry to assess and evaluate silicon and packaging technology offerings that provide PPA (power, performance, area) improvements in the SOC.

Actively participating in design-technology co-optimization (DTCO) for internal/external silicon technology, including understanding new technology strengths and limitations, identifying and driving cross discipline mega innovations that provide significant value for product. Including architecture, structural design, analog circuit design, power delivery.

Engaging with business unit engineering teams to understand product needs and translating them into foundry technology roadmap requirements.

Understanding package/board constraints in Si Construction along with yields, MFU aspects, and arriving at best disaggregation options for Chipsets/SOC products.

What we offer: We give you opportunities to transform technology and create a better future, by delivering products that touch the lives of every person on earth. As a global leader in innovation and new technology, we foster a collaborative, supportive, and exciting environment where the brightest minds in the world come together to achieve exceptional results. We offer a competitive salary and financial benefits such as bonuses, life and disability insurance, opportunities to buy Intel stock at a discounted rate, and Intel stock awards (eligibility at the discretion of Intel Corporation). We provide benefits that promote a healthy, enjoyable life: excellent medical plans, wellness programs, and amenities, time off, recreational activities, discounts on various products and services, and much more creative perks that make Intel a Great Place to Work. We're constantly working on making a more connected and intelligent future, and we need your help. Change tomorrow. Start today.

Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

The candidate must have a Master's degree in Electrical/Computer Engineering or a related field and 5+ years of experience -OR- a PhD in Electrical/Computer Engineering or a related field and 3+ years of experience in:

Knowledge Process/packaging technology assessment and benchmarking

Experience with SoC process definition and execution experience such as transistor selection, metal stack definition, area scaling, gate density improvement or DTCO

Knowledge of SOC/Chipsets circuit, structural design, package design knowledge

Strong transistor level understanding and characterization with reliability and failure mechanisms

Solid foundation knowledge of SOC design

Motivated, self-directed and skilled at working effectively both independently and as a team

Ability to work across the organization to achieve goals and thrive in a team-oriented environment

Preferred Qualifications:

Process technology benchmarking with external and/or internal Foundry

Design of analog circuits like PLLs, HSIOs, GPIOs, thermal sensors, is a plus

Post-silicon debugging experience

Technical leadership with good communication, interpersonal and problem-solving skills

Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Folsom Additional Locations: US, California, Santa Clara Business group: In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html

Annual Salary Range for jobs which could be performed in

US, California:$144,501.00-$217,311.00 S al ary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

#J-18808-Ljbffr