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Principal FPGA Design Engineer

San Diego, CA, United States

With nearly 80,000 employees globally, Kyocera is a leading manufacturer of high-tech Ceramics which are used in a variety of industries including aerospace, automotive, medical applications, and semiconductor processing.You will find our innovative materials in everything from smartphones to space shuttles!Check out our profile video!

Look at these PERKS !

Competitive pay, benefits, and hours

120 hours of vacation accrued per year to start (that's 3 weeks/year for regular 8-hour shifts!)

10 Paid Holidays per year

401(k)

401(k) company match

Pension

Medical insurance

Vision insurance

Life insurance

Flexible Spending Account (FSA)

Employee Assistance Program

We have a long-tenured staff (many with over 30 years of service!), a strong company mission, and an excellent benefits package that includes Medical, Dental, Vision, Life Insurance, Paid time off to Volunteer, paid Leave options,Tuition Reimbursement, and employer-paid Pension and a 401(k) with both Roth and a healthy company match.Many of our larger locations also feature onsite gyms, walking tracks, exercise rooms, and even employee gardens.

We strive to have a diverse workforce made up of people from all backgrounds, including minorities, women, and veterans, who bring their experience to support the innovation and quality that Kyocera is known for.

Kyocera International, Inc. also has a robust corporate culture and philosophy based on the experiences and writings of our founder, Dr. Kazuo Inamori, which you can learn more about here:https://global.kyocera.com/inamori/philosophy/ .Our company motto is “Do the right thing as a human being,” and we try to use that in our decision-making constantly.

Job Summary:

Principal FPGA Design Engineer will be responsible for developing Xilinx Synq RFSoC for the physical layer and ORAN processing for the Cellular Base Station. This is part of the KWIC 5G development.

Description of the Position

This position will collaborate with System, other FPGA, and firmware engineers for the development of RU. Responsibilities include RTL design development, simulation and implementation of the eCPRI interface, uplink, and downlink, PRACH signal processing flows and Xilinx IP primitive, development of the synchronization plane and management plane function and interface, interface to the embedded ARM cores and radio control software, interface to peripherals such as USB, SPI, I2C, DDR4, and others, and implement OTIC test cases. Primary engineer for the prototype bring-up, debugging, hardware bug tracking, and functional verification. Works proactively with other multi-functional teams to resolve optimum software solutions to improve the quality of the products.

Responsible to deliver high quality digital designs for the development of the FPGA design for the radio unit (RU) within a 5G NR Base station. Radio unit is based on the ORAN based split 7-2 architecture using Xilinx Zynq RFSoc for the eCPRI Ethernet interface, and lower physical layer 1 signal processing. It also contains embedded ARM cores and high speed ADC/DACs.

Pay Range: $160,000- $276,923.08 (Actual base pay based on factors such as relevant experience, education, market, qualifications, and skills)

REQUIREMENTS/QUALIFICATIONS

Bachelor’s degree is required, but we highly value Master’s or above. Relevant subject areas include Electrical Engineering, Computer Engineering, Computer Science, Math, Physics and other Engineering domains.

7+ years design experience with Xilinx RFSoc or MPSoc.

Good interpersonal and organizational skills.

Experience crafting RTL for high speed or multiple clock domain designs.

Hands-on experience debugging FPGA with integrated logic analyzer (ILA) and oscilloscopes.

Experience in modem or DSP algorithm developments in FPGAs or ASICs and successfully shipping products based on them.

Experience optimizing the segmentation of the design for a target FPGA, synthesizing for FPGA and implementing timing closure.

Experience with requirement specifications for PCB design and complex PCB bring up.

Familiar with Xilinx IP primitives and their interfaces.

Experience with Xilinx Vivado and Petalinux.

Experience with processing speed, power consumption optimization, and programmable logic resources optimization.

Familiar with cellular system layer 1 signal processing, OFDM waveform, FFT/iFFT, channel filtering, Nyquist sampling, NCO, multi-clock rate decimation/interpolation.

Familiar with petalinux and embedded arm core development.

Familiar with Ethernet, USB, SPI, I2C communication protocol and physical drivers.

Proficiency in the ORAN standards and OTIC test cases is a plus.

Proficiency in the 5G NR or LTE wireless communications standards is a plus

QUALIFICATIONS

Educational Background: MS or PhD degree in Electrical Engineering with strong background in mmWave RF, signal processing, transmission lines and beamforming antennas.

Industry Experience: 15+ years of industry experience in RF system design, including 5+ years of experience in mmWave basestation, CPE, or UE design.

Technical Skills: Proficiency in 5GNR, 3GPP requirements. In-depth knowledge of beamforming antenna, massive MIMO, modulator and demodulator architectures, analog and digital filtering, impact of modulated waveforms on performance, conductive and OTA calibration

Team Leadership: Demonstrated ability to lead and mentor teams, foster a collaborative work environment, and guide projects to successful completion.

Communication: Excellent written and verbal communication skills to effectively convey complex technical concepts to both technical and non-technical stakeholders.

PHYSICAL ACTIVITIES

The following physical activities described here are representative of those that must be met by an employee to successfully perform the essential functions of this job. Reasonable accommodations may be made to enable individuals with disabilities to perform the essential functions and expectations.

While performing the functions of this job, the employee is regularly required to sit, talk or hear; frequently required to walk; and occasionally required to stand, use hands to finger, handle, or feel, reach with hands and arms.

The employee must occasionally lift and/or move up to 25 pounds, frequently lift and/or move up to 10 pounds. Specific vision abilities required by this job include close vision.

ENVIRONMENTAL CONDITIONS

The following work environment characteristics described here are representative of those an employee encounters while performing essential functions of this job. Reasonable accommodations may be made to enable individuals with disabilities to perform the essential functions.

While performing the functions of this job, the employee is occasionally exposed to work near moving mechanical parts.

The noise level in the work environment is usually quiet.

ADDITIONAL INFORMATION

The above statements are intended to describe the work being performed by people assigned to this job. They are not intended to be an exhaustive list of all responsibilities, duties and skills required. The duties and responsibilities of this position are subject to change and other duties may be assigned or removed at any time. This position may require exposure to information subject to US Export Control regulations, i.e.: the International Traffic and Arms Regulations (ITAR) or Export Administration Regulations (EAR). All applicants must be US persons within the meaning of US regulations.

Kyocera International, Inc. values diversity in its workforce, and is proud to be an AAP/EEO employer. All qualified applicants will receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability.

If you are an individual with a disability and require a reasonable accommodation to complete any part of the application process or are limited in the ability or unable to access or use this online application process and need an alternative method for applying, you may contact Kyocera International, Inc. Human Resources team directly.

Reasonable accommodations may be made to enable individuals with disabilities to perform essential functions.

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Principal FPGA Design Engineer jobs in San Diego, CA, United States

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