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Apple
San Diego, CA, United States
Digital Layout Design Engineer San Diego,California,United States Hardware Do you have a passion for crafting entirely new solutions? As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from sc
Job Source: AppleApple, Inc.
San Diego, CA, United States
Summary Posted: Nov 9, 2023 Role Number: 200519471 Do you have a passion for crafting entirely new solutions? As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed, bringin
Job Source: Apple, Inc.INNOPHASE
San Diego, CA, United States
About InnoPhase, Inc. INNOPHASE is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA, and Bangalore, India. We are pioneering a revolutionary 5G platform that will transform cellular network deployments. Utilizing our breakthrough, patented, w
Job Source: INNOPHASEQualcomm
San Diego, CA, United States
Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > GPU ASICS Engineering General Summary: The Design Implementation Engineer will work in Qualcomm's Adreno GPU team and will be responsible for managing all aspect of front end implementation design challenges and methodology. As a member of the Graphics team, the s
Job Source: QualcommQualcomm
San Diego, CA, United States
Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > GPU ASICS Engineering General Summary: The Design Implementation Engineer will work in Qualcomm's Adreno GPU team and will be responsible for managing all aspect of front end implementation design challenges and methodology. As a member of the Graphics team,
Job Source: QualcommQualcomm
San Diego
**Company:** Qualcomm Technologies, Inc. **Job Area:** Engineering Group, Engineering Group > GPU ASICS Engineering **General Summary:** The Design Implementation Engineer will work in Qualcomm's Adreno GPU team and will be responsible for managing all aspect of front end implementation design challenges and methodology. As a member of the Graphics
Job Source: QualcommApple
San Diego
Digital Layout Design Engineer San Diego,California,United States Hardware Do you have a passion for crafting entirely new solutions? As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scrat
Job Source: AppleApple, Inc.
San Diego, CA, United States
Summary Posted: Feb 12, 2024 Role Number: 200464590 The Wireless SoC Radio Team designs state-of-art highly energy efficient CMOS radios, from RF to bits. To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filte
Job Source: Apple, Inc.San Diego, CA, United States
Job Description and Requirements
At Synopsys, we are at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. If you share our passion for innovation, we want to meet you.
In the System Solutions Group we are shaping solutions for dependable systems, requiring safety, security, reliability, low power and more. Our team works with customers and industry partners to understand their needs and identify technical requirements. We are passionate about methodologies and automation: we collaborate with customers to make their job easier when they develop their products.
Design Layout Implementation Engineer
We have an immediate opening for a Design Layout Implementation Engineer to join our team to work on the growing area of advanced packaging and multi-die design implementation. In this role you will be involved with the development of SOCs including hands-on work and providing technical leadership and guidance to internal or third-party SOC development teams. Using the industries most advanced place and route technologies, you will provide an end-to-end solution spanning from architecture and design partitioning to floorplan, route and implementation while working with a team of highly skilled thermal/electrical simulation engineers to optimize the design. You will work on and drive the progress of latest multi-die designs powering the most innovative GPUs and CPUs in the industry, while learning the latest technological advancements in the area of multi-die packaging such as CoWoS, InFO, 3DIC, etc...
Key Qualifications: BSEE/MSEE/PHD in Electrical and/or Computer Engineering
At least 5 years of experience in ASIC development.
Digital place and route. This includes floorplanning, clock tree synthesis and low power techniques
Experience either in SOC-level Architecture or SOC RTL development or as SOC Chip engineer
Knowledge of Synopsys EDA tools like 3DIC Compiler, IC Compiler II or Fusion Compiler or DC-NXT
Knowledge of front-end digital implementation is a plus. This includes RTL synthesis, STA
Proficiency in IC Compiler and/or Fusion Compiler
Will be able to travel on occasion for short periods of time, and occasionally work on-site at customer premises as required
Package layout experience is big plus
Preferred Experience:
2.5/3D packaging experience and knowledge of CoWoS, InFo, RDL... is a plus.
Has done multiple tapeouts in advanced nodes such as 16-/14-/10-/7-nm
Custom layout experience for analog and RF is a plus
Experience with chip-level thermal and EMIR analysis using Redhawk, generated CPM models, etc...
Has had direct customer interactions
Experience in designing SOC from Architecture to post-silicon
Experience working in a customer centric environment with great communication skills.
Ability to cross-functionally lead full SOC development from micro-architecture through GDS and work with partners on SW/FW and packaged parts full solution
Experience using workflow tools like git/gitlab/github is preferred
This position may include assignment to government contracts. Consequently, the ability to obtain government security clearances and/or other work clearances is preferred and will be required in the event of assignment to government contract work.
The base salary range across the U.S. for this role is between $133,000 to $206,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
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Email Alert for Design Layout Implementation Engineer jobs in San Diego, CA, United States
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