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ASIC verification Engineer

San Jose, CA, United States

Minimum Requirements: (“Must have” Qualifications)

1. At least 4 years of experience with pre-silicon DV (Design Verification)

2. Must have hands-on experience with writing code using System Verilog and UVM over the past 2 years

3. Must be a quick learner, independent and communicate well.

4. Knowledge and hands on experience with Verilog, System Verilog , UVM, debugging waveforms

5. Must be proficient with :

◦ building a testbench for a medium complexity block using System Verilog and UVM

◦ Writing random tests, directed tests, error tests & performance tests for a block of medium complexity using System Verilog and UVM.

◦ Developing, maintaining and supporting of the UVM verification environment.

◦ Debugging tests with design engineers to deliver functionally correct design blocks

◦ OOPS, randomization, constraints, interfaces

◦ writing & analyzing functional coverage, assertions

◦ Generating and analyzing code coverage & writing waivers

Desired Skills/Qualifications/System Experience requirements: (“Nice to have Qualifications”)

1. Experience with verification of networking products and networking background.

2. Experience with DMA based verification

Qualified candidates should send their resume and application to: [email protected]

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