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Intel
Phoenix, AZ, United States
Job Details: Job Description: As an ASIC Auto Place and Route APR Technology Development Engineer you will be responsible for, but not limited to the following: - Development of ASIC Auto Place and Route design flows and collateral using Synopsys Fusion Compiler and/or Cadence Innovus. - Perform detailed evaluation of tool run results to val
Job Source: IntelIntel
Phoenix, AZ, United States
Job Details: Job Description: Designs, develops, tests, and debugs software tools, flows, and methodologies used in design automation and by teams in the design of hardware products, process design, or manufacturing. Responsibilities include capturing user stories/requirements, writing both functional and test code, automating build and depl
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Phoenix, AZ, United States
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Job Source: Ciena CorporationHoneywell
Phoenix, AZ, United States
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Phoenix, AZ, United States
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Job Source: Eavx, Llc.Amazon
Phoenix, AZ, United States
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Job Source: AmazonHoneywell
Phoenix, AZ, United States
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Job Source: HoneywellPhoenix, AZ, United States
Job Details:
Job Description: As an ASIC Auto Place and Route APR Technology Development Engineer you will be responsible for, but not limited to the following:
- Development of ASIC Auto Place and Route design flows (including 3DIC Flows) and collateral using Synopsys Fusion Compiler and/or Cadence Innovus.
- Perform detailed evaluation of tool run results to validate proper tool behavior and identify root cause for any discrepancies found.
- Develop and enhance automation scripts for tool regression and quality.
- Generation and quality checking of APR tech files and other required tool collaterals.
- Develop and enhance automation scripts for collateral generation and quality.
- Develop and test Engineering Design Automation EDA tools and create flow scripts to analyze and test design methodologies.
- Designing, deploying and testing efficiency of tools in achieving design goals and collaborating with design teams on methodology development.
- Candidate should be willing to apply design methodologies to help execute projects effectively and successfully with high quality.
#DesignEnablement
Qualifications: You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Candidate must possess a BS degree with 3 + years of experience or MS degree with 2 + years of experience in Electrical Engineering or Computer Engineering or related field.
2+ years of experience in the following:
- ASIC standard cell design using Auto Place and Route (APR).
- ASIC Design Flows.
- TCL.
Preferred Qualifications:
3+ years of experience working with Perl, Python or Ruby.
2+ years of hands-on experience Extensive knowledge of Cadence Innovus, Synopsys Fusion Compiler.
1+ years familiarity with semiconductor design rules and physical verification
Job Type: Experienced Hire
Shift: Shift 1 (United States of America)
Primary Location: US, Arizona, Phoenix
Additional Locations:
Business group: As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
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ASIC Technology Development Engineer. jobs in Phoenix, AZ, United States
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