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Cadence Design Systems
San Jose, CA, United States
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The Cadence Compute Systems Group (CSG) develops and licenses IP designs for SoC and ASIC systems. This includes high-performance DSPs, CPUs, Interface IP, DDR controllers, hardware accelerators, and subsystems. Our cutting-edge compute eng
Job Source: Cadence Design SystemsSK hynix America
San Jose, CA, United States
Description Job Title : Principal / Sr. Principal Engineer - Pathfinding Design & Architecture Location : Sacramento or San Jose CA Job Type : Full-Time In the rapidly growing NAND Flash space amid the era of big data, this is an exciting time to be at SK Hynix NAND America. SK Hynix NAND America is looking for a talent that has a strong backgr
Job Source: SK hynix AmericaSK hynix America
San Jose, CA, United States
Description Job Title : Staff Engineer / Sr. Staff Engineer - Pathfinding Design & Architecture Location : Sacramento CA or San Jose CA Job Type : Full-Time In the rapidly growing NAND Flash space amid the era of big data, this is an exciting time to be at SK Hynix NAND America. SK Hynix NAND America is looking for a talent that has a strong ba
Job Source: SK hynix AmericaSamsung Electronics GmbH
San Jose, CA, United States
Staff Engineer, CPU / SoC Micro-architecture Job Title Staff Engineer, CPU / SoC Micro-architecture Job Location SSI San Jose Main Office Category Engineering - Hardware Job Type Full-time Job # 41937 Advancing the World’s Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehic
Job Source: Samsung Electronics GmbHConductor
San Jose, CA, United States
What You’ll Do The APL (Advanced Processor Lab) is one of the research team's of SAIT (Samsung Advanced Institute of Technology) which is Samsung‘s R&D hub, established as the incubator for cutting-edge technologies. SAIT’s mission has covered various research areas from AI applications/algorithms research, neuromorphic processor, domain-specific
Job Source: ConductorArray Labs Inc.
Palo Alto, CA, United States
Array Labs is building a distributed radar imaging constellation to power the first accurate, real-time 3D model of the world. The Hardware Engineering team at Array Labs is responsible for the analysis and design of our satellite and ground-station hardware platforms. These platforms tend to be a heterogeneous mix of various subsystems like comput
Job Source: Array Labs Inc.Esperanto-USA
Mountain View, CA, United States
Description We are looking for a Sr. SoC Physical Design Engineer with experience working on Top Level SoC Integration, IO Ring, Bump assembly, Power delivery, Clock planning, RDL Routing, IP integration as well as experience working on IP subsystems and Hierarchical blocks. This is an exciting opportunity to be part of a fast-paced Startup cultur
Job Source: Esperanto-USASQL Pager LLC
Sunnyvale, CA, United States
Principal/Senior Staff/Staff ASIC Design Engineer (RISC-V) Client Overview Client is building the first latency optimized SoC for their industry. Using its proven AI accelerator designs, Client is targeting best in class latency with order of magnitude improvements for years to come. Low Latency has become the key enabler for the industry and ot
Job Source: SQL Pager LLCSanta Clara, CA, United States
Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix's FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All of Achronix's products are supported by best-in-class EDA software tools.
Job Description/Responsibilities
Achronix is seeking an exceptional and proactive Principal/Sr. Staff Design Engineer to become an integral part of our forward-thinking Architecture and Design team, steering the development of the next generation FPGA. In this pivotal role, successful candidates will spearhead the design of a cutting-edge portfolio, encompassing on-chip networks, subsystems, and IP, all within the latest technology nodes. As a key player, the chosen individual takes charge of and actively contributes to the architectural vision, design execution, verification, and silicon validation processes, ensuring the seamless development of high-performance FPGA subsystems. If you're passionate about pushing the boundaries of technology and eager to leave your mark on the future of FPGAs, we invite you to join our dynamic team at the forefront of innovation.
Primary Job Responsibilities
Drive the architectural vision and design at the forefront of SoC development, taking charge of defining micro-architecture and specifications. Skillfully implement RTL using SystemVerilog and/or Verilog, showcasing expertise in integrating third-party IP at the SoC level through feasibility studies. Forge a collaborative partnership with the Verification team to define comprehensive test plans, execute tests, and adeptly debug designs.
Elevate your role by leading the development of performance models, actively participating in hardware and software system design reviews. Execute flows such as Lint, CDC, Synthesis, STA, and formal verification, while closely collaborating with the Backend team on critical aspects such as floorplan, Constraints definition, and timing analysis.
Your impact extends to supporting FPGA prototyping and post-silicon system bring-up, showcasing your commitment to the full lifecycle of hardware development. Foster a culture of collaboration by actively engaging with internal and external team members, contributing to architectural decisions, and influencing the continuous improvement of development flows and methodologies.
Required Skills
Proven experience in designing and seamlessly integrating on-chip networks with interconnect protocols like AXI, ACE, APB, etc.
Expertise in memory controllers and PHY layers, with a focus on DDR4/5, GDDR6, and HBM2/2e considered a significant advantage
Demonstrated expertise in Ethernet, including hands-on experience with priority-based flow control (PFC) and high-speed (100Gbps+) Ethernet, adding a distinctive edge
Recognized as an expert RTL developer with a strong background in SystemVerilog, utilizing ASIC development techniques and design flows at modern technology nodes, encompassing synthesis and timing closure
Strong knowledge in digital design involving multiple clock domains and clock power management
Proficient in low-power design, tools, and methodologies, including expertise in power intent UPF specifications, considered a significant advantage
Excellent communication and documentation skills, showcasing the ability to convey complex technical concepts with clarity and precision
Education and Experience
A minimum of 8+ years experience in SOC/ASIC front-end design
Bachelor or Master's degree in Computer or Electrical Engineering
The compensation range for this position is $120,000-$190,000. Salary ranges dependent on experience and location.
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Email Alert for Principal/Sr. Staff SOC Architecture and Design Engineer jobs in Santa Clara, CA, United States
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