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Tokyo Electron Limited
Austin, TX, United States
Senior ASIC Design Engineer page is loaded Senior ASIC Design Engineer Apply locations Austin / Headquarters time type Full time posted on Posted 3 Days Ago job requisition id R24-01853 Let’s search for your next career at TEL. Use the form below to search our current opportunities and then apply. Please cons
Job Source: Tokyo Electron LimitedChelsea Search Group
Austin, TX, United States
Senior Physical Design Engineer Austin, Texas (onsite/hybrid) US Citizen or US Permanent Resident 6-12 months contract with possible extensions Job Description : •7+ years of relevant experience in place and route •Able to handle top level, sub system level and block level timing analysis and fixes •Expert in TCL or Python scripting •For lead posi
Job Source: Chelsea Search GroupSambaNova Systems
Austin, TX, United States
The era of pervasive AI has arrived. In this era, organizations will use generative AI to unlock hidden value in their data, accelerate processes, reduce costs, drive efficiency and innovation to fundamentally transform their businesses and operations at scale. SambaNova Suite is the first full-stack, generative AI platform, from chip to model, op
Job Source: SambaNova SystemsProdapt ASIC services (Formerly Innovative Logic)
Austin, TX, United States
Prodapt is looking for a Senior Physical Design Engineer who has extensive experience in the RTL2GDSII flows for complex SoCs using the latest Synopsys/Cadence tools and nodes such as 5/3nm. 1+ year Contract Location: Austin, TX Responsibilities: Review block-level/top-level clock specifications for completeness and feasibility Handle all the Phys
Job Source: Prodapt ASIC services (Formerly Innovative Logic)Inspire Semiconductor, Inc.
Austin, TX, United States
InspireSemi is developing multi-thousand core RISC-V SoC’s for HPC & AI (High-Performance Computing), engineering/scientific, and graph analytics applications. In this position, the successful candidate will generate complete IC designs from RTL/netlists and third-party IP blocks, in the latest advanced FinFet process technology nodes. Job Respon
Job Source: Inspire Semiconductor, Inc.Apple, Inc.
Austin, TX, United States
Summary Posted: May 9, 2024 Weekly Hours: 40 Role Number: 200448191 At Apple we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a m
Job Source: Apple, Inc.Apple Inc.
Austin, TX, United States
At Apple we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportu
Job Source: Apple Inc.Voragotech
Austin, TX, United States
Do you love Space and want to leave your technical mark on exploring mankind’s next frontier? Does being a part of working with clients designing the next state-of-the-art spacecraft for near-earth orbit, Mars, Lunar and deep space explorations inspire you? Investment in Space organizations is at an all-time high, and you could have a seat at the t
Job Source: VoragotechAustin, TX, United States
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
The Compute Custom and Storage (CCS) team at Marvell is seeking candidates for a Senior Staff Static Timing Analysis (STA) engineering position. Common projects within CCS range from artificial intelligence and machine learning, to wired and wireless infrastructure, with the latest technology nodes. The team utilizes the latest EDA software tools, and work through the technical challenges to insure we meet the performance, power, and area requirements of the design. This position will work in tandem with the Physical Design, Design For Test, and other teams both at a local and global level. What You Can Expect
In this hybrid role at a CCS site, you will be a Timing Sub-System/Partition Lead, responsible for timing closure at your hierarchical level, and all blocks within
Work with design teams across various disciplines such as DFT, RTL, and IP in the process of iterative timing feedback and closure
Deliver to the SoC level all necessary collateral of your sub-system/partition per the required schedule
Conduct and adjust timing correlation between PD tools and signoff, along with participating in early feasibility studies
Provide pushdown timing ECOs to blocks within the sub-system/partition
Work closely with the block level PD engineers in debugging and resolving timing issues at their level, but also interface timing at the sub-system/partition level
Provide technical direction, coaching, and mentoring to employees on your team and others when necessary to achieve successful project outcomes
Write scripts in Perl, Python and TCL to extract data and achieve productivity enhancements through automation
Responsible for managing tool independent timing constraints that will work for synthesis, place & route and static timing analysis
What We're Looking For
Bachelor's degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience. OR Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.
3 years practical experience in Timing Analysis and Closure on multiple ASICs/SOCs, at a block and sub-system (ie. partition) level
Worked in the latest technology nodes, and experience in advanced timing concepts such as SI, CDC, LVF, POCV, and MIS
Good understanding of Verilog/VHDL, along with general digital logic and architecture
Proficient at running sub-system (ie. partition) level timing signoff
Proficient in UNIX, and shell based scripting
Knowledge and Experience in both TCL and Python languages
Have some proficiency in Synthesis and Physical Design
Diligent, detail-oriented, and able to handle assignments with minimal supervision
Must possess good communication skills, be a self-driven individual and a good team player
Familiar and experienced with the balancing the trade-offs of Performance, Power, and Area
Preferred Qualifications (in addition to the minimum qualifications)
5 years practical experience in Timing Analysis and Closure on multiple ASICs/SOCs, at a block and sub-system (ie. partition) level
Leading timing closure effort with a small team of engineers
Practical experience with Synopsys Timing Tools, such as Primetime and Tweaker
Experience in timing methodology and flow development
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Expected Base Pay Range (USD)
123,200 - 182,370, $ per annum The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process. This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [email protected].
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Email Alert for Senior Staff Engineer, Physical Design (STA) jobs in Austin, TX, United States
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