Silicon Design Verification Engineer_

Beaverton

We Are:

The Silicon Design group is a diverse team of world class silicon engineers. We have 100+ years of cumulative hands-on experience in architecture, logic design, verification, physical design, emulation and firmware. We use the latest silicon technologies and processes to help our clients create well-designed solutions to highly complex challenges. We are designing and developing next-generation, high performance SoCs, supporting our clients in their drive to deliver their product vision to their users. We are involved in all aspects of chip design from definition and architecture through to verification and signoff. Accenture engineers are true “Silicon to SW” Partners, allowing a new breed of companies in the semiconductor ecosystem to innovate in an unparalleled time to market.

You Are:

An experienced SoC Design Verification Engineer able to provide design verification services for multi CPU/DSP SoC.

The Work:

+ Testbench development - System Verilog UVM and C tests

+ Integration/development of C tests/APIs and SW build flow

+ Integration/development of UVM mailboxes and HW/SW communication components

+ Test plan development

+ Full working knowledge of Metric Driven Verification

+ Help with coverage closure, finding bugs and improving product quality

+ Power Aware testbench development and simulations

+ Seamless porting between simulation/emulation/prototyping platforms

+ Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto

+ Coverage collection and closure

+ Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope

+ Engage with the team to drive continuous improvement to the verification environment to find more bugs and improve coverage

+ Work as a team to grow together.

+ Mentor and coach junior team members

Here’s what you need:

+ A minimum of two years of experience with SoC Design Verification

+ Bachelor’s Degree or equivalent (12 years) work experience (If an, Associate’s Degree with 6 years of work experience)

Bonus points if:

+ Experience with PCIe and or CXL Verification

+ Experience with ARM Cortex and/or RISC-V processor verification

+ In-depth knowledge of digital logic design, chip architecture and microarchitecture

+ Experience in developing TestPlan/testbenches, SystemVerilog/UVM/C-based TestBench, and writing/debugging tests

+ Experience with advanced verification techniques such as different booting verification, end-to-end verification; multiple CPUs verification as part of the IP is desirable.

+ Experience in ARM AMBA protocols; AXI4, AHB and APB.

+ Team player with excellent communication skills and be able to work independently on the verification efforts for a block/area of the design

Compensation at Accenture varies depending on a wide array of factors, which may include but are not limited to the specific office location, role, skill set, and level of experience. As required by local law, Accenture provides a reasonable range of compensation for roles that may be hired in California, Colorado, District of Columbia, Maryland, New York or Washington as set forth below.We accept applications on an on-going basis and there is no fixed deadline to apply.

Information on benefits is here. (ccenture.com/us-en/careers/local/total-rewards)

Role Location Annual Salary Range

California $63,200 to $188,600

Colorado $63,200 to $163,000

District of Columbia $67,300 to $173,500

New York $58,500 to $188,600

Maryland $58,500 to $150,900

Washington $67,300 to $173,500

#LI-NA

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