Senior Layout Design and EDA Tools Engineer

Phoenix, AZ, United States

Job Details: Job Description: Designs, implements, and verifies the layout design of test structures and circuits which enable the development of Intel's leading-edge silicon technologies. The test structures are tailored to model Quality and Reliability (QnR) parameters which are essential to the qualification life cycle for each technology.

You will have the opportunity to work with partners in Technology Development (TD), Design Enablement (DE), and a world class team of QnR engineers to understand, define, and execute the requirements of new trailblazing Test Chips.

Primary responsibilities:

Develops custom layout design of analog blocks, complex digital, mixed signal blocks, standard cell libraries, or memory compilers (e.g., bitcells, SRAMs, Register Files).

Performs detailed physical array planning, area optimization, digital block synthesis, critical wire analysis, custom leaf, cell layout, and compiler assembly coding.

Conducts complete layout verification including design rule compliance, SoC integration specs, electron migration, voltage drop (IR), selfheat, ESD, and other reliability checks. Uses custom auto-routers and custom placers to efficiently construct layout.

Provides feedback to circuit design engineers for new feature feasibility studies and implements circuit enhancement requests.

Develops and drives new and innovative layout methods to improve productivity and quality.

Troubleshoots a wide variety of issues up to and including design and tool/flow/methodology issues used for layout design.

Additional responsibilities

Designs, implements, verifies, and supports the enablement and adoption of hardware design tools, flows, and methodologies.

Defines methodologies for hardware development related to technology node and EDA tool enabling.

Creates and verifies unique hardware designs, assembles design platforms, and integrates components into hierarchical systems to provide deployment coverage for end-to-end EDA tool testing on new technology nodes.

Develops, tests, and analyzes engineering design automation tools, flow, and methodologies to improve efficiency and optimize power and performance.

Supports development and enhancement of platforms, databases, scripts, and tools flows for design automation.

Builds deep understanding of digital design, verification, structural and physical layout, full-chip integration, power, and performance clocking, and/or timing to enhance future TFM development.

Collaborates with EDA vendors on defining and early testing of next-generation design tools.

Ideal Candidates will exhibit the following behavioral traits:

Strong initiative, analytical/problem solving skills.,

Team working skills.

Ability to multitask.

Able to work with a diverse team located in different geos.

Exceptional communication skills.

Willing to work effectively at all levels in an organization.

Willing to influence others and move toward a common vision or goal.

Familiarity with project management approaches, tools, and phases of the project lifecycle.

Flexible and adaptable; willing to work in ambiguous situations.

Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Bachelor's degree in Electrical/Computer Engineering or related field AND 6+ years of experience

OR

Master's degree in Electrical/Computer Engineering or related field AND 4+ years of experience

OR

PhD in Electrical/Computer Engineering or related field and 2+ years of experience.

REQUIRED EXPERIENCE FOR ALL THREE DEGREES:

CMOS VLSI design concepts, flows, and EDA tools.

Layout design, Cadence Virtuoso Layout Suite, layout debug (DRC, LVS).

Programming/scripting in C/C++, Python.

UNIX/Linux operating systems.

Preferred qualifications:

8+ years of experience in layout design, Cadence Virtuoso Layout Suite, layout debug (DRC, LVS).

4+ years of experience in EDA Tools, Flows, and Methodology (TFM) development

Experience leading and coordinating small/medium size group of layout designers.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Arizona, Phoenix Additional Locations: Business group: As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

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