Principal Engineer

Mountain View, CA, United States

Microsoft's hardware teams incubate advanced technologies and build deep partnerships with internal research, product planning, business, and marketing teams. Microsoft ships tens of millions of hardware products every year, including the Xbox, Surface devices, HoloLens, accessories, and much more. Our opportunities represent a variety of disciplines including, but not limited to, design, verification, performance modeling, and DevOps supporting the development of custom silicon. Microsoft’s hardware teams are also expanding into new technologies such as quantum computing! We are looking for the best and brightest to join us in designing for the future!

As a Principal Engineer, DFT (Design for Testability) in the Silicon Engineering and Solutions team, you will drive DFT solutions for the product and be at the center of chip design and enabling effort all the way from defining architecture, helping with implementation, ensuring verification coverage and finally with silicon bring-up and validation, for our projects. This will involve numerous projects within Microsoft developing custom silicon for a diverse set of systems. We are responsible for delivering cutting-edge, custom SoC designs that can perform complex and high-performance functions in the most efficient manner.

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positivelyimpactour culture every day.

Required/Minimum Qualifications

9+ years of related technical engineering experience OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience

OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience

OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.

9+ years demonstrated experience in DFT (design for testability) for VLSI (very large scale integration) design.

9+ in scan insertion, ATPG (automatic test pattern generation), MBIST (memory built in self-test), JTAG (joint test action group), IO (input/output) BIST, Scan Compression, and at-speed testing

Other Qualifications

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

Additional or Preferred Qualifications

15+ years technical engineering experience OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience

OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience

OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience.

Excellent debug skills for RTL and gate level simulations

Experience in DFT scan insertion and or Custom Memory BIST design and verification.

Ability to work independently and in a team setting and be able to research innovative solutions for business/technical problems

Solid technical aptitude and problem solving skills, take initiative, and be result driven debugging skills

familiar with Tessent DFT tools from Mentor Siemens.

Experience with industry standard simulation, ATPG and MBIST tools, particularly Mentor

Knowledge of defect types, fault models, silicon bring-up, debug and validation of DFT features on ATE

Experience with 3rd party HSIO (high speed input/output) DFT and verification of SERDES (Serializer/Deserializer) is a plus

Good communication and analytical skills

Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $133,600 - $256,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $173,200 - $282,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

Microsoft will accept applications for the role until April 29, 2024.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.

Design and develop scan insertion and memory BIST (built in self test) insertion, and test the silicon, debug and validate the DFT (design for testability) features on the ATE (automatic test equipment).

Improve the design, development, and overall quality of the hardware products and development processes.

Work on memory BIST design optimization to make sure design is time, power, and area efficient. Collaborate on a regular basis with memory unit owners for DFT architecture and flow development.

Develop methodology and flows for verification and debugging as well as anticipate and avoid blocking issues on projects. Develop ATE test patterns and algorithms to cover various memory and scan fault models. Work on infrastructure and test flow development for unit level and full chip verification.

Proactively identify new tools, technologies, and methods to do the job, and understand customer issues for DFT and BIST insertion. Analyze and compare different tools and methods and compare parameters such as area overhead, timing to optimize the DFT solution for the project.

Evaluate cost of DFT in terms of die are and test time, cost of memory diagnostics, and benefit of yield recovery for logic and memory redundancy.

Justify and show return on investment (ROI) for BIST and logic redundancy.

Measure repair rates of each chip and identify outlier memory designs that perhaps need circuit work or manufacturing improvement.

Other

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