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META
Sunnyvale, CA, United States
Summary: Meta is hiring ASIC Power Engineers within our Infrastructure organization to work on low level power designs. We are looking for individuals with experience in power modeling for ASICs (architecture to silicon), developing flows around EDA tools, and low-power design to build efficient System on Chip (SoC) and IP for data center applicati
Job Source: METAJuniper Networks
Sunnyvale, CA, United States
ENGINEERING- Juniper Networks in Sunnyvale, CA seeks ASIC Engineer: Define, architect, code, and deliver complex digital designs and verification suites/tests for ASICs. Develop block level verification environment using Universal Verification Methodology (UVM) and System Verilog. Part-time telecommuting allowed. $184,000/yr. - $211,200/yr. Email r
Job Source: Juniper NetworksJuniper Networks
Sunnyvale, CA, United States
ENGINEERING- Considering applying for this job Do not delay, scroll down and make your application as soon as possible to avoid missing out. Juniper Networks in Sunnyvale, CA seeks ASIC Engineer: Define, architect, code, and deliver complex digital designs and verification suites/tests for ASICs. Develop block level verification environment using
Job Source: Juniper NetworksJuniper Networks
Sunnyvale
ENGINEERING- Juniper Networks in Sunnyvale, CA seeks ASIC Engineer: Define, architect, code, and deliver complex digital designs and verification suites/tests for ASICs. Develop block level verification environment using Universal Verification Methodology (UVM) and System Verilog. Part-time tel...
Job Source: Juniper NetworksSQL Pager LLC
San Jose, CA, United States
Responsibilities: IP and/or chip level micro-architectures, implementation, and validation Develop algorithmic computation engines, NAND memory controller, and so on Write up micro-architecture and design document and be able to present to customers Develop RTL, perform synthesis, lint and CDC check Working with customers to trouble shooting, debug
Job Source: SQL Pager LLCMeta
Sunnyvale
**Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration. We are looking for talented individuals with deep experience that span one or more of the key areas required to build successful world-class complex SoC
Job Source: MetaCisco
San Jose, CA, United States
Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Ciscos silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and caf, social interest gro
Job Source: CiscoCisco Systems, Inc.
San Jose, CA, United States
The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco
Job Source: Cisco Systems, Inc.Sunnyvale, CA, United States
Meta is hiring ASIC Power Engineers within our Infrastructure organization to work on low level power designs. We are looking for individuals with experience in power modeling for ASICs (architecture to silicon), developing flows around EDA tools, and low-power design to build efficient System on Chip (SoC) and IP for data center applications.
ASIC Engineer, Power Responsibilities
Define the power specification at system and module level for Idle, TDP, Typical use cases.
Develop power modeling infrastructure in Python/C++.
Work with or develop architectural simulators in order to model performance and power.
Build power estimation flows at various levels of abstraction: C-model, RTL, Gate, Layout.
Optimize design for low-power with the understanding of system level concepts.
Evaluation and Implementation of low-power design techniques at different levels of abstraction.
Power characterization on silicon: idle, TDP, use case power & debug power issues on silicon.
Partner with vendors to drive low-power requirements for SoC interfaces such as LPDDR, PCIe, etc. Partner with EDA tool vendors to select and deploy the appropriate power estimation tools.
Collaborate with internal HW/SW Co-design, Architecture, Design, DV, and Emulation teams for power flows, optimization and estimation.
Minimum Qualifications Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.
3+ years of experience with modeling and design with C++/Python or an equivalent high level language.
Experience with EDA tools and scripting languages (Python, Tcl) used to build tools and flows for complex environments.
Preferred Qualifications Experience with architectural performance and power models at SoC and system level.
Understanding of ASIC design process and knowledge of leakage and dynamic power, and impact of environment and manufacturing process on power.
Knowledge of front-end and back-end ASIC tools.
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Email Alert for ASIC Engineer, Implementation jobs in Sunnyvale, CA, United States
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