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Apple, Inc.
Beaverton, OR, United States
Summary Posted: Nov 13, 2023 Role Number: 200520530 Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative t
Job Source: Apple, Inc.Apple, Inc.
Beaverton, OR, United States
Summary Posted: Jan 25, 2023 Role Number: 200458765 At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a results-oriented and extraordinarily talented Timing Design Engineer. As a member of our mul
Job Source: Apple, Inc.Intel
Hillsboro, OR, United States
Job Details: Job Description: Do Something Wonderful! Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let’s do something wonderful together. Join us, because at I
Job Source: IntelNVIDIA Corporation
Hillsboro, OR, United States
Senior Physical Design and Timing Engineer - Hardware page is loaded Senior Physical Design and Timing Engineer - Hardware Apply locations US, CA, Santa Clara US, MA, Westford US, TX, Austin US, OR, Hillsboro US, NC, Durham time type Full time posted on Posted Yesterday job requisition id JR1980492
Job Source: NVIDIA CorporationIntel Corporation
Hillsboro, OR, United States
SOC Design Engineer - Physical Design and Integration page is loaded SOC Design Engineer - Physical Design and Integration Apply locations US, Oregon, Hillsboro time type Full time posted on Posted 4 Days Ago job requisition id JR0263102 Job Details: Job Description: Performs physical design implementation o
Job Source: Intel CorporationWorkday
Hillsboro, OR, United States
Job Details: Job Description: Come join Intel's Client Engineering Group, responsible for designing Client SOCs that make up more than half of Intel's annual revenue. We envision the future of computing and design for the next generation of laptop and desktop computers. We are looking for an SoC (System on Chip) Physical Design Engineer, ready
Job Source: WorkdayIntel
Hillsboro, OR, United States
Job Details: Job Description: Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distributio
Job Source: IntelIntel GmbH
Hillsboro, OR, United States
Job Description Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability,
Job Source: Intel GmbHBeaverton, OR, United States
SoC Physical Design Engineer, STA/Timing
Beaverton,Oregon,United States
Hardware
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Submit Resume SoC Physical Design Engineer, STA/Timing
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**Summary**
Posted:Oct 23, 2023
Role Number: **200484347**
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it! Join us to help deliver the next groundbreaking Apple product. In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC using state of the art process technology.
**Key Qualifications**
+ Minimum BS and 10+ years of relevant industry experience.
+ Familiar with all aspects of timing of large high-performance SoC designs in sub-micron technologies.
+ Expert in STA and methodologies for timing closure, and have a deep understanding of noise, crosstalk, and OCV effects, among others.
+ Familiar with circuit modeling including SPICE models and worst-case corner selection.
+ Strong programming skills with Perl and TCL.
+ Experience with large design STA and Timing Closure.
+ Expert in ECO techniques and implementation.
+ Good communicator who can accurately describe issues, propose solutions, and drive them through completion.
**Description**
Work with design teams to understand and debug constraints, facilitate logic changes to improve timing. Work with Physical Design team, highlighting issues and best practices. Help create timing ECOs for project tapeout. Create and maintain scripts and methodologies for analysis and runs. Create documentation and help with guidelines/specs. Deep analysis of timing paths to identify key issues. Implement timing infrastructure.
**Education & Experience**
Minimum BS and 10+ years of relevant industry experience
**Additional Requirements**
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SoC Physical Design Engineer, STA/Timing jobs in Beaverton, OR, United States
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