Silicon Physical Design Engineer (STA)_

San Diego

We Are:

The Silicon Design group is a diverse team of world class silicon engineers. We have 100+ years of cumulative hands-on experience in architecture, logic design, verification, physical design, emulation and firmware. We use the latest silicon technologies and processes to help our clients create well-designed solutions to highly complex challenges. We are designing and developing next-generation, high performance SoCs, supporting our clients in their drive to deliver their product vision to their users. We are involved in all aspects of chip design from definition and architecture through to verification and signoff. Accenture engineers are true “Silicon to SW” Partners, allowing a new breed of companies in the semiconductor ecosystem to innovate in an unparalleled time to market.

You Are:

An experienced Physical Design/STA Engineer

The Work:

+ Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, constraints, static timing analysis, formal verification, Gate level functional & timing ECO in advanced technology nodes

+ Develop & document STA & Synthesis strategies. Interact with methodology teams to address challenges related to new technology nodes.

+ Familiar with constraint checking tools and techniques to deliver quality constraints for both pre and post CTS views.

+ Resolve design and flow issues related to physical design, identify potential solutions, and drive execution

+ Proficiency in advanced synthesis & STA techniques to achieve aggressive low power, area, and timing goals. Must be able to drive solutions for complex timing closure scenarios.

+ Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL transforms

+ Experience with multi-clock and multi-power domain designs.

+ Proficiency with ECO for functional and DFT timing closure

+ Deliver physical design of an end-to-end IP or integration of ASIC/SoC design

Here’s what you need:

+ A minimum of two years of experience with:

+ RTL2Gate experience on advanced technology nodes (7nm and below)

+ Low power implementation and signoff, power gating, multiple voltage rails, UPF knowledge

+ Block-level and full-chip integration

+ TCL, Python and/or Perl programming

+ EDA tools like DC/Genus, ICC2/Innovus, Primetime

+ Bachelor’s Degree or equivalent (12 years) work experience (If an, Associate’s Degree with 6 years of work experience)

Bonus points if:

+ Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs

+ Knowledge of static timing analysis, defining timing constraints and exceptions, corners/voltage definitions

+ Experience with Python, TCL or Perl programming

Compensation at Accenture varies depending on a wide array of factors, which may include but are not limited to the specific office location, role, skill set, and level of experience. As required by local law, Accenture provides a reasonable range of compensation for roles that may be hired in California, Colorado, District of Columbia, Maryland, New York or Washington as set forth below.We accept applications on an on-going basis and there is no fixed deadline to apply.

Information on benefits is here. (ccenture.com/us-en/careers/local/total-rewards)

Role Location Annual Salary Range

California $63,200 to $188,600

Colorado $63,200 to $163,000

District of Columbia $67,300 to $173,500

New York $58,500 to $188,600

Maryland $58,500 to $150,900

Washington $67,300 to $173,500

#LI-NA

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