STA Engineer

As an ASIC STA Engineer, you will be responsible for leading‑edge IP development and coordinating with multiple SOC teams. You will work collaboratively with various SOC teams to execute design and integration tasks for high‑quality IP deliverables across full chip and block level timing closure ownership throughout the entire project. You will develop and maintain methodology and flows related to timing verification and closure, generate block and full‑chip timing constraints, and work on Apple SoC chips in deep sub‑micron technologies targeting high‑end mobile applications. You will work closely with various multi‑functional teams on resolving complex timing issues for major building blocks of complex SoCs.

Minimum Qualifications

Bachelors Degree + 3 Years of Experience.

Preferred Qualifications

Strong fundamentals in the area of Digital design

Self-starter and highly motivated

Proficient in scripting languages (TCL and Perl)

Familiarity with ASIC design timing concepts

Exposure in STA tools (Primetime) is a plus

Familiarity with front end tools and methodologies such as Synthesis, Logic equivalence checks

Familiarity in Constraint analysis and debug, using industry standard tools such as Synopsys GCA (Galaxy Constraint Analyzer) is desirable but not required

Knowledge of timing corners/modes, process variations and signal integrity related issues is a plus

Ability to commnicate optimally across all internal groups

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